DAC 2026

Static timing analysis (STA) is crucial for Electronic Design Automation (EDA) flows but remains a computational bottleneck. While existing GPU-based STA engines are faster than CPU, they suffer from inefficiencies, particularly intra-warp load imbalance caused by irregular circuit graphs. This paper introduces Warp-STAR, a novel GPU-accelerated STA engine that eliminates this imbalance by orchestrating parallel computations at the warp level. This approach achieves a 2.4X speedup over previous state-of-the-art (SoTA) GPU-based STA. When integrated into a timing-driven global placement framework, Warp-STAR delivers a 1.7X speedup over SoTA frameworks. The method also proves effective for differentiable gradient analysis with minimal overhead.

Despite the existence of various automated PCB placement frameworks, the industry still relies heavily on human engineers. This is because these frameworks cannot perform placement according to specific user requirements and preferences, which limits their flexibility and industrial adoption. Moreover, the existing frameworks lack a modular perspective in placement, resulting in outputs that often perform poorly and fail to meet practical requirements. To address these problems, we propose ModuPlace, leveraging the powerful capabilities of LLMs to perform modular PCB placement with preference-optimized constraint graph generation. In ModuPlace, the entire component set is partitioned into modules at different granularities, enabling hierarchical and modular placement. Moreover, ModuPlace utilizes fine-tuning and preference optimization to enhance the quality of constraint graph generation and align the results with those of human experts. Experimental results demonstrate that ModuPlace outperforms all baselines, achieving superior placement quality across all metrics.

Sequential-constraint characterization consumes up to 80% of library signoff runtime. Traditional path-based methods rely on internal-node observability and fragile topology analysis, requiring extra simulations. They fail fundamentally for toggle-unexpected arcs such as hold and removal, where no robust internal voltage transitions exist. We present power-path, an internal-probe-free method that extracts a physics-grounded supply-current signature from the mandatory reference-delay simulation, enabling universal constraint estimation across all arc types without additional SPICE costs. An affine calibration using lookup table vertices refines the raw estimator for nominal characterization; for statistical deployment, an online ridge regression progressively tightens search intervals across Monte Carlo samples. Evaluated on post-layout TSMC 5 nm and 12 nm libraries across 5 PVT corners, power-path achieves 1.5× speedup with affine calibration and 3.6× with statistical calibration, while maintaining signoff-grade accuracy. The approach requires no topology analysis or additional simulations. We open-source our code and data.

In fault-tolerant quantum circuit synthesis, T gates supplied via magic states dominate space–time cost, while Clifford gates incur negligible overhead. Conventional flows minimize AND count in an {XOR, AND, NOT} basis as a proxy for T, which neglects phase cancellation and can be far from T-optimal. We instead formulate an exact T synthesis problem and canonicalize Boolean functions under Clifford equivalence. By precomputing T-optimal implementations up to seven variables and developing a specialized mapper, we reduce the T count by up to 16% on EPFL benchmarks and improve the best-known T counts of several cryptographic modules.

Dynamic Heterogeneous Graph Neural Networks(DHGNNs) effectively capture complex and evolving structural and semantic information through metapath learning. Despite notable advancements, current solutions still suffer from redundant metapath matching. To overcome these challenges, we introduce TDH-GNN, a topology-driven accelerator tailored for high-performance DHGNN inference. Specifically, we propose an efficient hyperedge-centric incremental execution approach into accelerator design, utilizing the concept of hyperedge to encapsulate dependencies among metapath instances, enabling incremental metapath updates and reducing redundant matching and computation. Implemented on a Xilinx U280, TDH-GNN delivers average speedups of 4.3x and 2.8x, along with 5.9x and 3.7x energy savings, over leading HGNN accelerators.

DNNs and LLMs increasingly rely on hardware accelerators, including in safety-critical domains, while technology scaling and growing model complexity make hardware faults more frequent. Existing system-level mechanisms typically treat the NPU as a monolithic unit, using coarse-grained replication that incurs prohibitive performance and hardware overheads, leaving a gap between reliability requirements and deployable solutions. To bridge this gap, we present Strix, a full-stack NPU reliability framework on an open-source SoC, spanning micro-architecture, ISA, and programming methods. Strix re-partitions the NPU along the system inference pipeline, identifies dominant failure modes, and attaches targeted safeguards, achieving sub-micro-second fault localisation, error detection, and correction with only 1.04x slowdown and minimal hardware overhead.

The combined effects of electromigration (EM) and IR drop critically affect the reliability and power integrity of power grids (PGs). Existing numerical methods are computationally prohibitive for large-scale designs, while most machine learning (ML) approaches analyze EM and IR drop in isolation, overlooking their shared physical structure and correlations in practical flows. To address this limitation, we propose GEMIR, a graph-based multi-task learning framework for the joint prediction of node-level static IR drop and edge-level EM-induced stress. GEMIR employs a cross-layer node-edge attention mechanism to effectively capture the mutual dependence between these two physical fields and integrates a physics-informed neural network (PINN) to enhance physical consistency in the EM path. Furthermore, we establish a composite optimization objective by incorporating physics-informed constraints that embed Kirchhoff's current law (KCL) and Korhonen's PDE to enhance model interpretability. To manage the inherently coupled yet sometimes conflicting optimization dynamics resulting from these constraints, we then develop a Conflict-Gated (CG) multi-task optimization that adaptively fuses or decouples task gradients based on their alignment, thereby achieving mutual optimality. Extensive experiments demonstrate that GEMIR outperforms existing single-task and multi-task baselines in accuracy and generalization. Specifically, it reduces the IR drop MAE by 40.79% and EM-induced stress RMSE by 19.35%, while maintaining high computational efficiency.

Graph neural networks (GNNs) are crucial for numerous applications, yet their huge computational demands often lead to suboptimal performance. Hyper-Dimensional Computing (HDC) is a brain-inspired learning approach for efficient and robust learning. HDC-based Graph Learning (HDGL) shows significant improved computational efficiency and accuracy by learning graph representations in a high-dimensional space. Despite these advantages, general-purpose computing platforms such as CPUs and GPUs are insufficient for efficiently handling HDGL tasks. In this paper we propose an accelerator called HDGAS through algorithm and hardware co-design for HDGL. Based on the insight that not all node features in a graph are equally important, we propose to jointly optimize a lightweight filter with the HDGL model to dynamically identify and eliminate less significant node features during runtime. Moreover, we design a specialized system architecture for end-to-end HDGL acceleration, harnessing the proposed dynamic sparsification technique in tandem with the inherent SpMM operations within HDGL. Extensive experiments demonstrate that HDGAS achieves $6.76\times$ ($69.31\times$) speedup and $7.58\times$ ($80.12\times$) energy-efficiency improvements over GNN accelerators (GPU).

3D Gaussian Splatting (3DGS) has emerged as a popular representation technique for efficient novel view synthesis due to its explicit Gaussian-based formulation. However, achieving real-time rendering at 90 frames per second (FPS) remains challenging. Prior hardware accelerators have explored custom ASIC or FPGA implementations that deliver higher performance than GPUs, but these designs often rely on advanced technology nodes (e.g., 7nm) and substantial on-chip storage, which significantly increase deployment cost and limit practicality. Meanwhile, existing studies largely overlook the potential of modern GPUs, as the 3DGS pipeline lacks native General Matrix Multiplication (GEMM) operations, which are essential for utilizing Tensor Cores. In this paper, we propose GEMM-GS, a GPU acceleration framework that enables efficient 3DGS execution on Tensor Cores through a GEMM-compatible reformulation of the blending stage. GEMM-GS transforms the original blending process into matrix-multiplication-friendly operations and incorporates a high-performance CUDA kernel with a three-stage double-buffered pipeline to overlap computation and memory accesses. The design is plug-and-play on commodity GPUs, requiring no hardware modifications and thus ensuring practical deployability. Experimental results demonstrate that GEMM-GS achieves a $1.42\times$ speedup over the baseline 3DGS implementation and provides an additional $1.47\times$ average speedup when integrated with existing acceleration techniques.

Graph partitioning is essential for many EDA applications that leverage task graph parallelism for faster execution. For instance, RTL simulators partition an input RTL design into dependent tasks and schedule them across threads. However, existing partitioners are largely limited to general-purpose heuristics that overlook real threading costs, resulting in suboptimal performance. Consequently, we introduce DiffPart, a differentiable task graph partitioning framework that automatically learns high-quality partitions under real operating conditions. Applied to RTL simulation, DiffPart improves state-of-the-art Verilator's partitioning quality, delivering up to 1.22--55.25x faster simulation runtime across diverse designs.

In advanced packages, large power/ground (P/G) planes are essential for power integrity but prone to warpage. While a uniform metal-density constraint combats warpage, mandatory degassing holes complicate adherence and degrade IR-drop. We propose BLADE, the first P/G plane synthesis methodology that enforces this constraint while optimizing power integrity. BLADE expands P/G planes from skeletons under metal density control to ensure connectivity, naturally leaving holes for degassing. Guided by a fast IR-drop evaluator, our bi-level Bayesian optimization framework efficiently navigates the design space. Experiments on six SiP cases demonstrate that BLADE satisfies the metal-density constraint and achieves superior IR-drop performance.

Circuit Representation Learning (CRL) offers a powerful paradigm to guide and optimize core Electronic Design Automation (EDA) tasks, but its practical adoption is hindered by the immense scale of industrial netlists and a failure to explicitly model register-level temporal dynamics. To overcome these barriers, we introduce DeepSeq3, a novel hierarchical framework that abstracts circuits into a two-level representation: fine-grained combinational subgraphs partitioned by flip-flops (FFs), and a high-level Super-Node Graph (SNG) that models the register-transfer structure. A dual Graph Neural Network (GNN) architecture learns representations at both levels, capturing local Boolean logic and global state transitions. Crucially, we introduce a state-centric pre-training scheme that predicts the reachability between FF states, endowing the model with a deep understanding of temporal behavior. Demonstrated on large-scale benchmarks, DeepSeq3's approach yields superior scalability and richer representations, reducing bounded model checking (BMC) solving time by 18% while guaranteeing correctness. Our code is avaiable at https://anonymous.4open.science/r/DeepSeq3-6760

High-level synthesis (HLS) has been widely adopted to map high-level languages to hardware, significantly improving hardware design productivity. Existing HLS tools have gaps in generating custom hardware due to data dependencies and differences in intermediate representation (IR) levels. Appropriate IRs can be created for each by separating the algorithmic behaviour and the microarchitecture description, which is an effective way to reduce development costs and achieve competitive hardware designs. In this paper, we propose DataFlowGen, an open-source framework built on MLIR for efficient dataflow accelerator generation. DataFlowGen explicitly introduces a two-level IR to perform operations at suitable abstraction levels, capturing dataflow characteristics and multi-level hierarchy. Leveraging these representations, we develop an automated optimizer that outlines the application kernel and performs dataflow transformations to derive a hardware-oriented control dataflow graph (H-CDFG). It enables concise representation and resource efficiency of hardware architectures. Experiments show that DataFlowGen achieves a performance improvement with significant resource reduction compared to state-of-the-art HLS tools. The results show that our optimizer effectively leverages the expressive power of IRs thus capturing kernel parallelism.

Mixture of Experts (MoE) improves LLM expressiveness without proportional compute, yet its large parameter footprint hinders deployment in storage- and latency-constrained environments. Existing pruning methods attempt to reduce redundancy but often suffer severe accuracy loss at high pruning ratios due to limited pruning metrics. To tackle this challenge, we propose **KL-MoE**, a hierarchical pruning framework based on KL divergence scoring mechanism. KL-MoE first clusters experts by the similarity of experts. Then we develop a **KL-based Scoring** mechanism to retain the most representative expert within each cluster by jointly capturing the *local* and *global* functionality. In addition, we introduce the **Linear Restore** strategy, a lightweight mapping strategy that refines the outputs of the pruned MoE layer to approximate the original layer, thus recovering the accuracy of the pruned models. Extensive experiments across multiple models and tasks demonstrate that KL-MoE yields average gains of **12.89%**, **7.24%** and **6.14%** over state-of-the-art methods O-Prune, MoE-I$^2$ and HC-SMoE, respectively, while delivering a 1.31x inference speedup. Our code is available at https://anonymous.4open.science/r/KL-MoE-a.

Approximate Nearest Neighbor (ANN) search is a foundational primitive for AI applications such as Retrieval-Augmented Generation (RAG). CPU and GPU-based solutions face scalability bottlenecks due to limited local memory, while a multi-tier architecture using SSDs introduces high latency from coarse-grained I/O, mismatched with fine-grained data access patterns inherent to ANN search. We present CANNON (A CXL-Based Near-Memory Processing Architecture for Approximate Nearest Neighbor Search on Real Hardware), a fully offloaded Near-Memory Processing (NMP) architecture implemented on real CXL hardware. CANNON transforms the ANN search pipeline into a fine-grained, deeply pipelined dataflow architecture to maximize throughput, and introduces asynchronous hashing, a speculative execution mechanism that hides hash-check latency to prevent pipeline stalls. Evaluated on large-scale vector datasets, CANNON achieves up to two orders of magnitude performance improvement over state-of-the-art CPU and GPU baselines.

Mixture-of-Experts (MoE) large language models (LLMs) leverage dynamic routing and sparse activation to improve efficiency and scalability, achieving high performance with reduced computational cost. However, their complex architecture and large memory footprint pose significant challenges for deployment, particularly on resource-constrained hardware. Post-training quantization (PTQ) is a widely used technique to reduce model size and memory usage. Existing PTQ approaches for MoE models are predominantly layer-wise and task-agnostic, optimizing reconstruction error independently within each layer. As a result, they ignore cross-layer differences in expert importance and fail to leverage task-specific signals, causing pivotal experts to be over-compressed, rarely activated experts to be over-provisioned, and overall accuracy to degrade. To overcome these limitations, we propose ExQuant, a PTQ framework for MoE LLMs that enables global, expert-level mixed-precision quantization. ExQuant first constructs a Globally Comparable Expert Importance Metric by integrating expert routing frequency and post-ablation performance. Based on this metric, it assigns tiered bit-widths to experts and employs a precision-aware load balancing strategy to dynamically schedule computation across processing elements, fully exploiting slack between low- and high-precision workloads. Experiments demonstrate that ExQuant significantly reduces memory footprint, improves inference efficiency, and achieves $2.87-5.93\%$ accuracy improvement over existing MoE quantization methods. These results validate the effectiveness of global, expert-level mixed-precision quantization for efficient and accurate deployment of MoE LLMs.

Point-based Neural Networks (PNNs) have become a key approach for point cloud processing. However, a core operation in these models, Farthest Point Sampling (FPS), often introduces significant inference latency, especially for large-scale processing. Despite existing CUDA- and hardware-level optimizations, FPS remains a major bottleneck due to exhaustive computations across multiple network layers in PNNs, which hinders scalability. Through systematic analysis, we identify three substantial redundancy in FPS, including unnecessary full-cloud computations, redundant late-stage iterations, and predictable inter-layer outputs that make later FPS computations avoidable. To address these, we propose FlashFPS, a hardware-agnostic, plug-and-play framework for FPS acceleration, composed of FPS-Prune and FPS-Cache. FPS-Prune introduces candidate pruning and iteration pruning to reduce redundant computations in FPS while preserving sampling quality, and FPS-Cache eliminates layer-wise redundancy via cache-and-reuse. Integrated into existing CUDA libraries and state-of-the-art PNN accelerators, FlashFPS achieves 5.16× speedup over the standard CUDA baseline on GPU and 2.69× on PNN accelerators, with negligible accuracy loss, enabling efficient and scalable PNN inference.

Dynamic-shape neural networks are essential for handling variable-length data in tasks, but their optimization is challenging. Existing methods, such as hand-tuned libraries or static kernel compilation, are inefficient due to a lack of flexibility or the high overhead from repeated compilations. We propose DyTuner, an adaptive operator-level tuning framework for dynamic-shape neural networks. DyTuner uses a unified, system-compatible interface and an adaptive algorithm to efficiently tune kernels for varying shapes, significantly improving end-to-end performance and reducing redundant compilations. Experiments demonstrate that DyTuner effectively optimizes dynamic-shape workloads, achieving speedups of up to 1.41x and 1.64x over state-of-the-art solutions, BladeDISC and TorchInductor.

The scaling-up of large language models (LLMs) necessitates computing systems to have multi-processor-chip architectures, elevating the importance of chip-to-chip (C2C) communication. However, designing efficient C2C hardware architectures for LLM workloads faces three key challenges: generating realistic LLM-specific C2C traffic, accurately simulating hardware-level communication at scale, and efficiently exploring the exponentially large C2C design space. We propose C2C-Explorer, an adaptive Bayesian DSE framework that integrates a LLM-workload-driven traffic generator, a scalable interconnect simulator (switch/full-mesh, up to 512 chips), and a metric-guided evaluator into a workload-to-hardware optimization pipeline, enabling systematic C2C architectural co-design under realistic LLM workloads. Validated against FPGA-based C2C prototypes, the C2C simulator achieves 2.46–8.23% end-to-end timing error across diverse traffic patterns. Its hybrid cycle & event model further accelerates large-scale simulation by up to 7.8× over a pure cycle-accurate baseline. Applied to a 32-XPU DeepSeek-R1-671B inference workload, C2C-Explorer identifies configurations that improve goodput by 44.1% and reduce memory by 98.4%. C2C-Explorer is open-source and available at https://anonymous.4open.science/r/C2C-Explorer.

Thermal management critically affects the reliability of chiplet-based heterogeneous integrated circuits in the post-Moore era. The design process demands hundreds of thermal simulations across varying power distributions, cooling conditions, and structural configurations. Conventional methods based on finite element methods (FEM) and compact thermal model (CTM) lack the flexibility for efficient multi-scenario evaluations and incur prohibitive computational cost when modeling complex vertical stacks with cross-scale interconnects. We propose LegoTherm, a modular thermal modeling framework that decomposes chiplet-based systems into reusable reduced-order components. The framework exploits the inherent hierarchical structure of heterogeneous integration to construct high-fidelity 3D meshes capturing micro-interconnection details through modular discretization, then generates reduced-order modules by aggregating thermally coupled interface ports. This approach preserves critical hotspot accuracy while enabling rapid reassembly for different design scenarios. Evaluated on industrial-scale 2.5D and 3D packaging benchmarks, LegoTherm achieves up to 10.39X speedup compared to COMSOL while maintaining mean relative error below 0.40%. The framework reduces thermal design iteration cycles from weeks to half a day, addressing a critical bottleneck in modern IC design.

Sparse matrix multiplication (SpGEMM) is fundamental various applications, yet conventional processors suffer from poor parallelism due to bandwidth limitation and pipeline stalls . Therefore, we propose PF-GEMM, an accelerator exploiting hardware parallelism with three key methods. Firstly, we introduce a novel sparse format named prefix-CSR (PFCSR), which merges redundant prefixes of nearby indices to reduce I/O amount. Further, with element-wise out-of-order scheduling, PFGEMM achieves locally optimal data reuse to avoid pipeline stalls. Finally, PF-GEMM's cache employs a frequency-aware replacement policy to extend data residency. Overall, experiments demonstrate a gmean of 1.8x off-chip traffic reduction and 2.1x speedup over state-of-the-art accelerators.

Register-Transfer Level (RTL) verification is a primary bottleneck, consuming 60–70% of development time. While Large Language Models (LLMs) show promise for RTL automation, their performance and research focus have overwhelmingly centered on RTL generation rather than verification. Current methods for RTL verification rely on large-scale proprietary models (e.g., GPT-4o) to generate Python-based functional references, incurring a high cost and raising data-privacy risks. To date, an end-to-end open-source solution for autonomous verification remains absent. We introduce PRO-V-R1, the first trainable open-source agentic framework for autonomous RTL verification. Our contributions are threefold: (1) we design PRO-V sys, a modular agentic system that couples LLM-based reasoning with programmatic tool use for RTL verification; (2) we establish a data construction pipeline that leverages existing RTL datasets to build simulation-validated, expert-level trajectories tailored for supervised fine-tuning (SFT) RTL verification agents; and (3) we implement an efficient reinforcement learning (RL) algorithm that uses verification-specific rewards derived from program-tool feedback to optimize the end-to-end verification workflow. Our empirical evaluation demonstrates PRO-V-R1 achieves a 57.7% functional correctness rate and 34.0% in robust fault detection, significantly outperforming the base model's 25.7% and 21.8% (respectively) from the state-of-the-art (SOTA) automatic verification system. This configuration also outperforms large-scale proprietary LLMs in functional correctness and shows comparable robustness for fault detection.

Fault-tolerant quantum computing relies on low-depth and high-fidelity syndrome extraction in quantum error correcting codes. We propose a scheduling strategy for syndrome extraction circuits in the broad class of quasi-abelian lifted-product codes, encompassing both hypergraph product and bivariate bicycle codes. Our approach constructs syndrome extraction circuits with CNOT depths no more than one layer above the fundamental lower bound, frequently achieving optimal depth. A pipelined variant further reduces the average depth per round, and the strategy generalizes naturally to higher-dimensional product codes. This scheduling framework enables computational speedups for quantum computing architectures built on these codes, all while preserving high-fidelity error correction.

Low-bit large language models (LLMs) use quantization to compress weights to 1/2/4 bits, significantly shrinking model size while preserving accuracy. Existing work leverages the reduced precision to cut computation. However, roofline analysis on the NVIDIA A100 shows limited inference speedup even with a 6.7× reduction in computation.This limitation is caused by insufficient memory bandwidth. Processing-in-memory (PIM) provides a promising solution for the memory bottleneck by integrating compute near data. To support efficient low-bit LLM inference, PIM should be carefully designed with joint software and hardware optimizations. This paper presents FreeBit, a PIM-based architecture that unleashes the performance potential of low-bit LLMs. The objective is to capture the low-bit nature to better exploit PIM through hardware-software co-design. At the hardware level, a lookup-table (LUT)-centric architecture is designed to support quantized computation and minimize redundant computation. A sparsity-aware memory optimization is introduced to optimize memory access and leverage PIM bandwidth. At the software level, a static-dynamic decoupled scheduling strategy is presented to exploit PIM parallelism. Experimental results show that FreeBit effectively reduces redundant computation and memory access, and delivers notable performance improvements over CPUs, GPUs, and prior PIM baselines.

Triple Sparse General Matrix-Matrix Multiplication (TriSpGEMM) is a major performance bottleneck in scientific computing and graph analytics. Existing domain-specific accelerators support only Sparse General Matrix-Matrix Multiplication (SpGEMM). Performing TriSpGEMM by sequencing two SpGEMM kernels introduces a global synchronization barrier, forces intermediate data to be written to and read from off-chip memory, and leads to frequent pipeline stalls, all of which significantly degrade performance. A natural solution is to design a fused architecture that executes TriSpGEMM directly, but such a design must overcome three key challenges, i.e., pipeline overflow caused by highly irregular and bursty sparse dataflows, locality inefficiency stemming from the trade-off between input reuse and output aggregation, and severe head-of-line blocking due to variable memory access latencies. In this work, we present TRIDENT, a transient-data-centric accelerator for fused TriSpGEMM processing. TRIDENT integrates a hierarchical flow-control mechanism, a hybrid dataflow co-designed with a windowed sparse format, and an out-of-order decoupled execution scheme to ensure pipeline stability, locality efficiency, and latency tolerance. Comprehensive evaluations demonstrate that TRIDENT achieves an average of 3.56x performance speedup over state-of-the-art SpGEMM accelerators, and up to 49.6x and 6.3x improvements over CPU and GPU baselines, respectively.

Processors are the foundation of all computing systems, yet complex RTL and microarchitectural front ends make logic defects difficult to eliminate and extremely costly to fix after tape-out.Although RISC-V fuzzing has revealed many bugs in practice, existing approaches remain limited: they rely on manually maintained instruction models and generate insufficiently rich CPU test programs.Moreover, they lack precise register and memory monitoring, and either perform high-overhead per-instruction differential checks or coarse end-of-program comparisons -- both making bug analysis and localization inefficient. In this work, we propose RISCSmith (30K+ Rust LoC), a fuzzing framework aimed at detecting bugs in RISC-V CPUs.First, RISCSmith automatically builds rich instruction models by parsing the RISC-V UnifiedDB to extract structured instruction metadata, resolve inconsistencies, and generate strongly typed models capturing operand roles and runtime semantics.Second, RISCSmith instruments RISC-V implementations with lightweight logging to collect per-instruction register, memory, and exception data, performing on-the-fly differential analysis to pinpoint the first divergence, classify its cause, and minimize the reproducing test case.We implemented and evaluated RISCSmith on six widely used RISC-V CPUs. In total, it uncovered 18 previously unknown bugs.Compared to state-of-the-art CPU fuzzers like Cascade and RISCV-DV, RISCSmith detects 3.5x and 2.6x more bugs and covers 37% and 61% more branches, respectively.

SRAM-based compute-in-memory (CIM) offers high computational density and energy efficiency for deep neural network (DNN) accelerators, but its limited capacity causes on/off-chip data movement overhead for large DNN models. Existing CIM accelerator studies typically assume that DNN models fit entirely on-chip, leaving efficient dataflow design largely untapped. This paper introduces AccelCIM, a systematic dataflow exploration framework for SRAM CIM accelerator, which addresses two key limitations of prior work. (1) It formulates a systematic dataflow design space spanning CIM macro configurations and macro-array organizations. (2) It introduces rigorous design evaluation using cycle-accurate architectural simulation and post-layout PPA analysis. We conduct an extensive design space exploration and apply AccelCIM to representative LLM applications, providing practical insights for the principled design of CIM accelerators.

Large neural surrogate models accelerate scientific simulation but still face scalability limits from model size and memory. We present FP-DDM (Foundation-model-based Physics-guided adaptation for the Domain Decomposition Method), a scalable framework for large-scale physics analysis. FP-DDM divides the domain into overlapping subdomains and enforces interface consistency by explicitly optimizing boundary values on overlaps via automatic differentiation, enabling fast alignment. Specifically, we propose a foundation architecture that effectively learns multi-physics and trasfer new domain. The combination of foundation-model adaptation and physics-guided test-time adaptation enables generalization to new physics and unseen domains without labels. On thermal and stress problems, FP-DDM achieves numerical-solver-level accuracy, scales to 10-billion-cell domains, and supports layout design optimization, establishing its potential as a multi-physics platform for next-generation System–Technology Co-Optimization.

This work presents ROSA, a microring-based optical neural network architecture that improves robustness and energy efficiency using an optical shift-and-add (OSA) module and a layer-wise hybrid mapping strategy. It introduces a noise-aware voltage-to-weight model considering DAC and thermal variations, and a workload-aware framework to co-optimize MRR array size and layer-wise dataflow. Optimized arrays reduce aggregated relative energy-delay-product (EDP) by 64% and 26%, compared to DEAP-CNNs and general compact array respectively. OSA further contributes 29% EDP reduction. The proposed hybrid mapping strategy improves CIFAR-10 accuracy by 8.3% than weight-stationary mapping while achieving an average 54.7% lower EDP than DEAP-CNNs.

Asynchronous Traffic Shaping (ATS) bounds end-to-end delay in Time-Sensitive Networking (TSN) without relying on global synchronization, but its per-group queuing introduces inter-flow interference that causes large delay jitter for time-critical flows. To address this limitation, we present PFATS, a novel per-flow asynchronous traffic shaping architecture that integrates a per-flow frame eligibility time calculator, per-flow queues, and a Synchronous Shift Register Matrix (SSRM) scheduler. We implement PFATS on an FPGA-based TSN switch, and it supports 192 flows by incurring only 7.14% additional on-chip memory usage compared to conventional ATS. In realistic TSN scenarios, PFATS achieves microsecond-level end-to-end delay and bounds delay jitter within 5 μs, while maintaining high throughput.

IoT messaging protocols face critical security risks from behavior bugs - specification violations that enable unauthorized data access and device compromise. Detecting such bugs requires comprehensive understanding of protocol specifications and communication semantics. This paper introduces ARES, a fully automated framework that extracts executable behavior oracles from protocol specifications for real-time compliance monitoring using LLM-driven behavior filtering. ARES evaluates six widely-used IoT protocol implementations, identifying 25 new bugs with 87.5% precision, including 21 behavior bugs. Of these, 18 have been confirmed or fixed and 10 CVEs assigned due to their severity.

Emerging device characteristics modeling is indispensable for potential circuit design integration. In the modeling process, the Verilog-A language is employed, leveraging the physical parameters and test results of the device. This work demonstrates the large language model (LLM) empowered Verilog-A iterative (LLMVA) for the modeling process of spin-transfer-torque magnetic-tunnel-junction (STT-MTJ). LLM enhances the quick interaction with device-level characteristics and circuit-level indicators, and realize design technology co-optimization (DTCO). In macro level, the 4-Mb 28-nm magnetic-random-access-memory (MRAM) macro is designed and then tape-out. To the best of the authors' knowledge, this is the first work to use LLM for device modeling and MRAM DTCO. The iterative test results show that the deviation between Front-test/Post-test results of MTJ does not exceed 9.2%, proving the effectiveness of the proposed LLMVA modeling process. With the proposed LLMVA agent, we have decreased our designer and time cost by about 50%.

Learning to compute, the ability to model the functional behavior of a circuit graph, is a fundamental challenge for graph representation learning. Yet, the dominant paradigm is architecturally mismatched for this task. This flawed assumption, central to mainstream message passing neural networks (MPNNs) and their conventional Transformer-based counterparts, prevents models from capturing the position-aware, hierarchical nature of computation. To resolve this, we introduce TRACE, a new paradigm built on an architecturally sound backbone and a principled learning objective. First, TRACE employs a Hierarchical Transformer that mirrors the step-by-step flow of computation, providing a faithful architectural backbone that replaces the flawed permutation-invariant aggregation. Second, we introduce function shift learning, a novel objective that decouples the learning problem. Instead of predicting the complex global function directly, our model is trained to predict only the function shift, the discrepancy between the true global function and a simple local approximation that assumes input independence. We validate this paradigm on various circuits modalities, including Register Transfer Level graphs, And-Inverter Graphs and post-mapping netlists. Across a comprehensive suite of benchmarks, TRACE substantially outperforms all prior architectures. These results demonstrate that our architecturally-aligned backbone and decoupled learning objective form a more robust paradigm for the fundamental challenge of learning the functional behavior of a circuit graph.

Recent advances in Microsoft's ternary BitNet, restricting weights to {-1, 0, +1}, have highlighted the potential of low-bit large language models (LLMs). Ideally, each ternary weight requires only log_2(3), approximately 1.58 bits. However, existing inference systems still use redundant bit representations for computational efficiency. To push the compression boundary and maintain efficiency, we propose TernaInfer, a GPU inference framework for ternary LLMs that integrates lossless compression with ternary-optimized sparse matrix multiplication. To our knowledge, TernaInfer is the first work to realize 1.58 bits per weight on the ternary BitNet while providing 1.53 times throughput improvement over half-precision GPU inference.

Edge computing that offloads AI inference from the cloud to local devices can significantly reduce interaction latency and improve data privacy, while simultaneously imposing stringent requirements on both efficiency and security. Non-volatile compute-in-memory (nvCIM) boosts efficiency by executing multiply-accumulate (MAC) inside memory arrays, reducing data movement and eliminating weight refresh. However, deploying nvCIM in untrusted environments exposes both user inputs and model weights to multiple security threats: during storage, non-volatility keeps weights vulnerable to physical extraction; during computation, plaintext inputs must be transferred and exposed at runtime. Recent in-memory encryption CIM (IME-CIM) schemes integrate an XOR cipher and in-situ decryption to protect stored weights, yet still require plaintext keys and inputs during inference and often incur up to 2x array area overhead, leaving a security-efficiency gap. This paper proposes S²CIM, a FeFET-based nvCIM architecture with circuit-algorithm co-design to bridge this gap. For security, an Affine-Transform Splitting (ATS) scheme based on randomization strategies protects both offline weights (XORed weights) and online computation (obfuscated inputs) without explicitly exposing plaintext keys or inputs. For efficiency, a Drain-Input Gate-Scan (DIGS) based on 1FeFET-1R achieves low-variation signed multi-bit MAC in minimal cycles with high area efficiency comparable to common nvCIMs. We validate its functionality using an S²CIM macro with 16x16 arrays. Compared with recent IME-CIMs, S²CIM improves area efficiency by up to 16.8x and reduces energy per MAC by up to 6.7x, while ensuring 97.4% encrypted ViT inference accuracy and reducing attack success rates to 50% under all potential threat models.

Inverse lithography (ILT) is critical for modern semiconductor manufacturing but faces the challenge of non-convex optimization, which can lead to sub-optimal local minima. Although advances in model architectures and loss functions have improved performance and reduced the number of post-ILT refinement iterations, two critical issues remain unresolved, leaving generative AI–based inverse solutions sub-optimal: 1) The training dataset is often sub-optimal; simply mimicking its behavior does not necessarily yield higher-quality masks. 2) Post-training ILT refinement involves navigating a highly non-convex manifold. To address this, we reformulate the generative model G as a learned distribution over the mask space conditioned on designs. Using a Style-Aware GAN pre-trained on a large design dataset, we introduce a fine-tuning stage that combines policy optimization with imitation learning. This trains the GAN to generate masks that are both high-quality and robust, requiring minimal subsequent numerical refinement. Our hybrid framework mitigates the sub-optimal traps of conventional ILT, improves mask quality, and reduces optimization time, offering advantages beyond what traditional solvers can achieve.

Scaling fault-tolerant quantum computing is increasingly constrained by the limited bandwidth and power budget across the 4\,K-room temperature (RT) interface. We present CryoZip, a cross-layer cryogenic compression framework that cooperates with an lightweight in-house quantum error correction (QEC) predecoders to reduce syndrome transmission under realistic, circuit-level noise. CryoZip targets sparse syndrome vectors with a sliding-window compression architecture sized under strict decoding-latency constraints to maximize energy efficiency. We implement and evaluate the design in 22\,nm FDSOI characterized at 4\,K, using vector-based power, performance, and area analysis to obtain realistic hardware data. CryoZip achieves up to 48.3$\times$ compression---1.81$\times$ higher than state-of-the-art compressors---across various QEC codes; when paired with the predecoder it yields over 14,238.86$\times$ bandwidth reduction (48.3$\times$ without predecoding), and delivers 3.97-25.74$\times$ energy savings for cryo-to-RT links alone, rising to 42.19$\times$ when accounting for predecoding and realistic QEC interface overheads.

Multicore processors are increasingly adopted in embedded systems to meet growing performance demands. However, physical side-channel analysis of multicore architectures remains underexplored, as obtaining usable leakage is inherently challenging. Consequently, side-channel security research on such systems has lagged far behind, leaving a critical security gap. To address this gap, we reveal the electromagnetic leakage mechanisms in multicore architectures and, for the first time, demonstrate per-core leakage exploitation, thereby enabling physical side-channel analysis for these systems. As a practical extension, we present a non-intrusive side-channel monitoring method that achieves per-core granularity. To validate its feasibility and practicality, we implement a prototype on a heterogeneous SoC platform with an RF front-end, and evaluate on a commercial off-the-shelf quad-core embedded system, the Raspberry Pi 4B with ARM Cortex-A72 cores.

Logic Equivalence Checking (LEC) is often bottlenecked by synthesis-induced structural perturbations and XOR-dense regions that hinder SAT solving. We contend that the *modeling* of the miter is as critical as the SAT solver itself and propose a miter-aware mapping framework that reformulates the problem before solving by constructing a LUT-based miter preserving structural correspondence and exposing high-level logic relations. It integrates equivalence-preserving mapping, Gaussian-guided XOR modeling, and solver-oriented LUT selection to produce solver-efficient representations. Experiments on comprehensive benchmarks show up to 92.1% reduction across state-of-the-art SAT solvers, highlighting the importance of solver-aware modeling in enhancing LEC efficiency.

Recent advances in GPU-accelerated hypergraph partitioning have achieved substantial performance gains but remain limited to full partitioning. In particular, the lack of support for incrementality is a critical limitation for being used by many CAD applications, where circuit hypergraphs iteratively undergo incremental modifications as part of optimization loops. To overcome this limitation, we present iHyperG, the first GPU-parallel incremental k-way hypergraph partitioner. iHyperG introduces a scalable delta-based hypergraph data structure for efficient incremental modifications on a GPU, along with an effective incremental partitioning algorithm that rebalances partitions in a single pass and refines only cut-critical vertices. Experimental results show that iHyperG achieves average speedups of 190x for modification and 83x for partitioning over a state-of-the-art GPU-parallel hypergraph partitioner, while maintaining comparable partitioning quality.

CPUs are critical for LLM serving due to their availability, cost efficiency, and edge applicability. However, efficient CPU serving is hindered by conflicting prefill/decode resource demands under non-disaggregated deployment constraints—existing solutions fail to avoid cross-phase interference, ignore sub-NUMA hardware structures, and deliver suboptimal dynamic-shape kernel performance. We propose Sandwich, a full-stack CPU LLM serving system with three core innovations addressing these challenges: (1) seamless phase-wise plan switching to eliminate cross-phase interference; (2) TopoTree, a tree-based hardware abstraction for automated substructure-aware (e.g., LLC slices) partial core allocation; (3) fast-start-then-finetune dynamic-shape tensor program generation. Evaluated on five x86/ARM CPU platforms, Sandwich achieves average 2.01× end-to-end speedup and up to 3.40× latency reduction over SOTA systems. Its kernels match static compiler performance with three orders of magnitude less tuning cost.

Stochastic computing (SC) enables compact and low-complexity hardware but remains underexplored for vision applications. We propose EdgeSC, a unified stochastic framework that extends edge detection to diverse and composite operators. Pixel intensities are encoded as stochastic bitstreams, and gradients are computed through finite-state machines (FSMs) ensembles operating in the probability domain. A differentiable MUX mapping learns operator-specific behaviors without changing the architecture. Fabricated in 28-nm CMOS, EdgeSC achieves 15.9$\times$ smaller area, 4.4$\times$ lower power, and 6.3$\times$ better area-delay product than 8-bit baselines while maintaining comparable accuracy and throughput.

Mining temporal motifs in temporal graphs is essential for many critical applications. Despite several software/hardware temporal motif mining solutions have been proposed, they still suffer from substantial redundant and irregular off-chip communications due to misaligned search tree expansions across different motif matching tasks. In this work, we observe that different tasks traverse the same temporal graph edges in strict chronological order, exhibiting strong data locality among these tasks. Motivated by this insight, we propose LTMiner, a locality-aware hardware accelerator designed to efficiently handle temporal motif mining. Specifically, LTMiner proposes a novel chunk-based search tree expansion mechanism into the accelerator design to align the graph traversals of different tasks at the granularity of data chunks, substantially boosting the data locality among these tasks for lower data access cost. The results show that LTMiner gains 1.1×–652.6×, 1.8×–70.3× speedups and 3.9×–2050.9×, 1.2×–17.3× energy savings compared to the cutting-edge software and hardware solutions, respectively.

Printed circuit board (PCB) design is increasingly critical as artificial intelligence (AI) systems demand higher integration density and stricter electrical constraints, while purely manual workflows struggle to keep up. We introduce PCBgen, a spec-to-schematic framework that integrates PCB knowledge graph (PCB-KG)-based retrieval, constraint-aware pre-filtering, a multi-modal intermediate representation (IR), and SPICE-in-the-loop, training-free Group Relative Policy Optimization (TF-GRPO) into a unified closed-loop pipeline for board-level design. This pipeline compresses an otherwise combinatorial search space (up to 10^20 candidates) to roughly 10^3 simulatable designs while preserving semantic and electrical validity. Extensive experiments for power supply designs demonstrate that, on a 336-case benchmark spanning six topology families and three design regimes, PCBgen improves topology adaptation (TA) by up to 57%, raises Pass@5 from 41% to 74%, and cuts token usage and wall-clock time by more than 50% compared with LLM-only baselines. In a 24-case comparison with human designers using existing vendor tools, it achieves 3.70x and 4.74x speedups in topology selection and schematic verification with comparable Pass@1, yielding an overall return on investment (ROI) of 4.39x and pointing toward a practical route to agentic, closed-loop PCB power supply design.

NVIDIA's Multi-Instance GPU (MIG) technology, which enables reconfiguration of large GPUs into smaller, independent slices, is a promising feature for high-performance AI inference servers. Our characterization reveals that the data preprocessing stage of AI inference causes a significant performance bottleneck in these MIG-based inference systems. We present PREBA, a hardware/software co-design targeting MIG inference servers. PREBA offloads data preprocessing to a latency-optimized, FPGA-based accelerator. Simultaneously, PREBA's analytical model-based dynamic batching system maximizes small vGPU utilization by creating optimal, input-aware batches. PREBA provides 3.7x improvement in throughput, 3.5x energy-efficiency, and 3.0x cost-efficiency over a baseline that uses CPU-based preprocessing.

The Mixture-of-Experts (MoE) architecture has emerged as a promising approach to mitigate the rising computational costs of large language models (LLMs) by selectively activating parameters. However, its high memory requirements and sub-optimal parameter efficiency pose significant challenges for efficient deployment. Although CPU-offloaded MoE inference systems have been proposed in the literature, they offer limited efficiency, particularly for large batch sizes. In this work, we propose SpecMoE, a memory-efficient MoE inference system based on our self-assisted speculative decoding algorithm. SpecMoE demonstrates the effectiveness of applying speculative decoding to MoE inference without requiring additional model training. Our system improves inference throughput by up to 4.30×, while significantly reducing bandwidth requirements of both memory and interconnect on memory-constrained systems.

Diffusion Transformer (DiT)-based video generation models (VGMs) achieve state-of-the-art visual quality through global attention mod- eling but incur heavy computational overhead due to the quadratic complexity of attention. In high-resolution or long-duration videos, attention often dominates inference latency. However, much of this computation is redundant—many attention scores contribute little to the output and can be safely skipped or approximated. Fully exploiting this redundancy requires (1) identifying important re- gions in large attention maps, (2) determining adaptive retention ratios across heads and blocks, and (3) handling scores of varying importance efficiently. We present HierPAS, a hardware–software co-optimized design that accelerates VGMs using hierarchical pre- cision and adaptive sparsity. HierPAS employs a lightweight eager attention method to estimate attention patterns and a sampling- based entropy analysis to derive head-wise retention ratios with minimal cost. It applies progressively reduced precision to less critical regions and integrates a configurable top-𝑘 engine with a unified multi-precision GEMM engine supporting multiple preci- sions in one datapath. Evaluations show that HierPAS improves energy efficiency by up to 178×over NVIDIA H20 and 7.7×over state-of-the-art accelerators, with negligible loss in video quality.

Adiabatic Quantum-Flux-Parametron (AQFP) is a promising superconducting logic family that combines ultra-low power consumption with high-speed switching. However, the extensive insertion of buffers and splitters (B/S) to satisfy fan-out and synchronization constraints significantly increases circuit area and depth, becoming a key bottleneck in AQFP synthesis. Existing heuristic approaches are lightweight but prone to local optima, while global or exact methods achieve higher solution quality at the expense of runtime and scalability. In this work, we propose the first Large Neighborhood Search (LNS)-guided framework for AQFP B/S insertion, which combines multi-granularity group movement with a destruct-and-repair paradigm to systematically escape local minima while ensuring legality through constraint-aware repair. Extensive experiments on ISCAS'85 and EPFL benchmarks show that our framework achieves up to 14.0% fewer B/S insertions and 13.1% fewer junctions on large EPFL circuits, while yielding the lowest circuit depth among state-of-the-art methods. It also attains up to a 3.1× runtime speedup on large benchmarks, and on the ISCAS'85 suite reduces B/S and JJs by 13.0% and 8.1% respectively.

Low-batch LLM inference on edge hardware places stringent demands on both memory bandwidth and computational capacity. While 3D-stacked DRAM accelerators offer a promising solution, they introduce two critical overheads that are frequently under-optimized: DRAM refresh and collective communication. To mitigate these issues, we propose 3D-ReSAC, a near-memory processor based on 3D-stacked DRAM, equipped with an area-efficient sequential refresh-skip method and high-link-utilization ArrowMesh communication. Our evaluations show that 3D-ReSAC reduces refresh and communication overheads by 7–100% and 53–75%, respectively, leading to a 1.12× to 2.02× latency reduction across low-batch LLM inference workloads.

As modern CPUs grow increasingly configurable, design space exploration (DSE) has become essential for navigating complex architectural trade-offs. However, existing DSE approaches predominantly rely on statistical correlations, resulting in opaque decision processes. They cannot clearly explain the underlying causes of how configurations affect PPA outcomes, which in turn reduces designers' confidence in automated recommendations. To address this limitation, we introduce causal learning into the DSE pipeline and develop CAL-DSE, a framework that constructs a validated causal graph combining statistical evidence with LLM-informed domain knowledge. Building on this structure, the causal graph decomposes the high-dimensional design space, enabling both interpretability and efficient exploration. Experimental results on RISC-V processor show that CAL-DSE achieves up to 4.12× hypervolume improvement while revealing validated causal pathways between design parameters and PPA outcomes.

Zero-knowledge proofs (ZKP) enable verification without revealing private data, but proof generation remains compute-intensive, dominated by polynomial (POLY) and elliptic-curve (EC) operations over large-bitwidth fields. Efficient acceleration requires flexible multi-precision arithmetic and high utilization across shifting POLY and EC workloads, yet existing reconfigurable designs address these demands only partially. We propose ZK-Flex, a software–hardware co-designed framework that reduces computation through hardware- and workload-aware POLY and EC optimizers, and employs TCore, a Toom–Cook–based multi-precision core supporting diverse bitwidths. Across representative benchmarks, ZK-Flex delivers 5-11x speedup and up to 3.8x higher area efficiency than prior accelerators.

Automated standard cell library extension is crucial for maximizing Quality of Results (QoR) in modern VLSI design. We introduce CellE, a novel framework that leverages formal methods to achieve exhaustive discovery of functionally equivalent subcircuits. CellE applies equality saturation to the post-mapping netlist, generating an e-graph to cluster all functionally equivalent implementations. This canonical representation enables an efficient pattern mining algorithm to select the most area-optimal standard cells. Experimental results show a 15.41% average area reduction (up to 23.64% over prior work). Furthermore, characterization in a commercial flow demonstrates an 8.00% average delay reduction, confirming CellE's superior QoR optimization capabilities.

Though quantum computing theoretically provides exponential computational advantage, an end-to-end quantum speedup should consider the encoding, compilation, and many other peripheral process that rely on classical computer. Among them, the readout error mitigation turns out to be the bottleneck, requiring mitigation of noise errors to achieve high fidelity. To this end, leveraging the sparsity in the tensor-product has emerged as an appealing approach to improve computational efficiency. However, existing approaches, based on intermediate data pruning or threshold pruning, suffer from the limited accelerator and fidelity loss. In this paper, we propose SiTA a quantum error mitigation accelerator that exploits the inherent sparsity of Hilbert space. The key insight lies in that the superposition states generated by quantum algorithms cover only a subset of the Hilbert space (output sparsity), and the basis state naturally exhibits bit-level sparsity (input sparsity). Therefore, we introduce a sparse dataflow that features probability-level and state-level parallelism, which effectively skips calculations related to zero values. Finally, we design its hardware architecture that supports various computational paradigms of tensor-product, enabling acceleration for readout error mitigation. Experiments show that SiTA achieves an end-to-end speedup of 4.9X to 1605X over prior mitigation methods, without sacrificing fidelity.

Hybrid-bonding 3D DRAM (HB-DRAM) delivers massive in-situ bandwidth but shifts LLM accelerator bottlenecks from off-chip memory to the Network-on-Chip, where decentralized bank-local bandwidth must be coordinated across arrays. We present HiBand, a bandwidth-aware HB-DRAM accelerator that co-designs array-level execution with a four-mode reconfigurable NoC. HiBand combines grouped tensor parallelism and cross-head array-level co-execution to confine most traffic to short-range links while overlapping bandwidth-bound attention with compute-bound feed-forward layers. On LLM models mapped to a 32-array HB-DRAM accelerator, HiBand achieves up to 4.28× speedup over an HBM3 GPU-style accelerator and 1.67× speedup over a state-of-the-art HB-DRAM–based NMP design.

The propositional Satisfiability (SAT) problem is fundamental to many applications in Electronic Design Automation (EDA). This paper presents PRS, an efficient and comprehensive parallel SAT framework. We introduce two key techniques to enhance solver performance. The first is a lightweight preprocessing method called Resolution Checking, which efficiently simplifies circuit-encoded CNFs. The second is a new hybrid diversification strategy that combines a Regular Shifting method for the initial branching order with a parallel local search to generate diverse initial variable phases. PRS also supports extensive preprocessing, dynamic clause sharing, reproducible parallel solving, and parallel proof generation. Extensive experiments on the SAT Competition 2025 (SC25) benchmark demonstrate the effectiveness and scalability of our framework: PRS outperforms the SC25 Parallel-Track winner MallobSAT by solving 12 more instances with an 11.4% better PAR2 score, while also achieving a 4.7x speedup on 64 cores.

Combinational Equivalence Checking (CEC) is a cornerstone of modern IC design and verification flows, and state-of-the-art CEC solvers predominantly rely on SAT-sweeping frameworks. As circuit scale and complexity continue to increase, purely serial sweeping becomes a critical performance bottleneck, motivating the exploration of parallelism. However, existing parallel CEC approaches primarily focus on accelerating the verification of individual candidate pairs, while leaving the sweeping process itself essentially serial. This paper presents HydraCEC, a novel, general-purpose parallel CEC framework that, to the best of our knowledge, is the first to parallelize the sweeping process itself by concurrently executing its verification tasks. Its effectiveness is further enhanced by a dynamic benefit-aware scheduling policy guided by a Task Benefit Graph (TBG), and an asynchronous equivalence sharing mechanism that enables cooperation without global synchronization. Experimental results on ISCAS/ITC, Datapath, and Large-Scale benchmarks show that HydraCEC consistently outperforms existing parallel CEC solvers, particularly on large-scale instances, where it achieves a 10.5x speedup over the best competitor and exhibits excellent scalability, reaching 72.3x speedup with 128 cores.

Large Language Model (LLM) serving is crucial for applications like chatbots and code assistants, yet its implementation remains bottlenecked by low hardware utilization. Speculative decoding improves effective throughput, but still suffers from suboptimal resource partitioning. We introduce SmoothSpec, a speculative decoding system designed to maximize serving throughput by fully leveraging intra-device parallelism. SmoothSpec deploys draft and target models with the same parallelism configurations but allocates asymmetric compute resources at runtime. We design a novel scheduling strategy that dynamically adjusts both the draft parameters for the next step and the resource allocation ratio between the two models, based on the generation quality of draft tokens. We implement SmoothSpec on a single-node LLM serving system and demonstrate its effectiveness across diverse workloads.

Building high-performance Spiking Neural Networks (SNNs) involves a trade-off among competing paradigms. While unsupervised rules like STDP offer efficiency and ANN-to-SNN conversion provides a simple path, direct training with Backpropagation Through Time (BPTT) is the most effective route for achieving high accuracy. However, BPTT's effectiveness comes at a steep price: its memory cost scales linearly with timesteps, creating a resource barrier that limits the information capacity and practicality of SNNs. This makes \emph{memory-efficient} training methods critical for real-world deployment. To this end, we propose the \underline{Ski}pping-\underline{S}ide-\underline{T}uning (SkiST) framework, which leverages both spatial and temporal redundancy in SNNs for \emph{memory-efficient} fine-tuning. On the spatial side, SkiST introduces side networks and applies low-rank approximation with adaptive rank filtering to compress trainable parameters. On the temporal side, it employs Dynamic Sparse BPTT, selectively skipping non-critical timesteps during gradient propagation while compensating for information loss with exponentially decayed gradients. Experiments show SkiST reduces GPU memory by up to 50\% over full fine-tuning while maintaining competitive accuracy. On an SNN-based language model, SkiST requires 23.2\,GB of memory for 1024-token sequences, compared to 40.3\,GB for the baseline, with minimal accuracy degradation. This work enables the deployment of adaptable, efficient spiking models on resource-constrained devices.

As post-quantum cryptographic (PQC) schemes are standardized, evaluating their resilience to side-channel attacks (SCA) becomes critical. While most prior studies focus on physical SCAs, the practicality of remote SCAs on full implementations of standardized PQCs remains largely unexplored. In this paper, we present the first generic remote power SCA on the Module-Lattice-Based Key Encapsulation Mechanism (ML-KEM), evaluated on a modern Intel x86 processor. Our result demonstrates that power traces can be exploited remotely as a plaintext-checking oracle, enabling secret key recovery despite the scheme's theoretical IND-CCA security. Using ML-KEM as a case study, we show that complex microarchitectural mechanisms such as speculative execution and dynamic power management do not eliminate exploitable power leakage. We evaluated our attack on the PQClean implementation, achieving secret key recovery with a success rate up to 99.5%. These findings provide a realistic assessment of PQC leakage behavior on high-end processors and underscore the need for architecture-aware leakage models and co-designed hardware–software defenses to ensure secure PQC deployment in practice.

Ethereum's massive data requires auxiliary proofs (e.g., Merkle proofs) for trusted queries, creating significant I/O and data movement overhead. We introduce EtherSSD, an innovative in-storage Ethereum analytics platform with computational storage devices (CSDs) designed for real-time data analysis. EtherSSD bridges the semantic gap between the host and CSDs, dissolving authenticated data queries into flattened (highly concurrent) in-CSD page accesses with slashed I/O operations from the host side. Additionally, EtherSSD incorporates an authentication engine that offloads cryptographic verification computations from host CPUs. Evaluations under real-world workloads demonstrate that it reduces authenticated query execution time, particularly the I/O and authentication overhead.

This paper reveals and exploits a critical security vulnerability: the electromagnetic (EM) side channel of capacitive touchscreens leaks sufficient information to recover fine-grained, continuous handwriting trajectories. We present Touchscreen Electromagnetic Side-channel Leakage Attack (TESLA), a non-contact attack framework that captures EM signals generated during on-screen writing and regresses them into two-dimensional (2D) handwriting trajectories in real time. Extensive evaluations across a variety of commercial off-the-shelf (COTS) smartphones show that TESLA achieves 77% character recognition accuracy and a Jaccard index of 0.74, demonstrating its capability to recover highly recognizable motion trajectories that closely resemble the original handwriting under realistic attack conditions.

As VLSI designs grow in complexity, partitioning is widely adopted to accelerate physical design through parallel computing. However, traditional hypergraph partitioning methods often degrade in performance when applied to 2D layouts due to spatial constraints. For routers with post-placement locations, a spatial-aware partitioning method fully utilizing placement data is preferable. Existing works can only consider soft spatial constraints, leading to a scattered distribution in one partition. We propose SAAP, an analytic partitioning algorithm enforcing hard spatial constraints while efficiently minimizing cut sizes. It includes analytic boundary modeling with regularity-guided simulated annealing and region embedding. Given placed netlists, it generates timing-friendly k-way spatially continuous partitions for parallel routing. Experiments show that it can quickly provide several to dozens of times smaller spatial cut sizes than previous state-of-the-art, with better spatial continuity.

Backside power delivery networks (BSPDN) provide superior power integrity while freeing backside routing resources. However, existing works fail to fully exploit these resources for power, performance, and area (PPA) optimization through strategic net allocation. This paper presents a co-optimization framework that maximizes PPA by strategically routing both clock and signal nets on the backside, enabling double-side routing. Experimental results demonstrate 88.1% IR-drop reduction, 23.0% frequency improvement, 10.9% power savings, and timing improvements (66.3% WNS, 40.2% TNS) over FSPDN with negligible nTSVs overhead.

Graph Neural Networks (GNNs) offer powerful graph-structured data modeling capabilities, yet their acceleration is challenging. Rigid hardware parallelism struggles to accommodate algorithmic diversity and the sparse, irregular topology inherent to GNNs. To resolve this conflict, we propose TAG, a topology-aware GNN accelerator that achieves high performance through synergistic innovations at three levels: dataflow, scheduling, and memory hierarchy. For algorithmic diversity, we employ a configurable, topology-driven dataflow that is aware of both algorithmic needs and graph structure. To mitigate irregularity, a contention-aware scheduler orchestrates irregular memory access by reordering them into a conflict-free stream. Furthermore, an algorithm-architecture co-designed memory hierarchy, combined with a coarse-to-fine graph partitioning algorithm, maximizes data reuse from sparse graphs and significantly minimizes off-chip traffic. Evaluations demonstrate that TAG achieves an average of 3.22x speedup and 3.04x energy efficiency over state-of-the-art GNN accelerators.

Disk-based Approximate Nearest Neighbor Search (ANNS) suffers from high I/O latency due to random node access, which dominates over 90% of search time. To address this, we propose SpecANNS, an In-Storage Computing (ISC)-based solution leveraging in-storage FPGAs for fast distance computation. SpecANNS speculatively identifies pages likely to be accessed in subsequent hops and exploits NAND flash parallelism to minimize page read latency. Implemented on real Computational Storage Device (CSD) hardware with a simple interface, SpecANNS significantly reduces query latency and improves energy efficiency compared to state-of-the-art disk-based ANNS methods.

As processor designs grow more complex, verification remains bottlenecked by slow software simulation and low-quality random test stimuli. Recent research has applied software fuzzers to hardware verification, but these rely on semantically blind random mutations that may generate shallow, low-quality stimuli unable to explore complex behaviors. These limitations result in slow coverage convergence and prohibitively high verification costs. In this paper, we present Lyra, a heterogeneous RISC-V verification framework that addresses both challenges by pairing hardware-accelerated verification with an ISA-aware generative model. Lyra executes the DUT and reference model concurrently on an FPGA SoC, enabling high-throughput differential checking and hardware-level coverage collection. Instead of creating verification stimuli randomly or through simple mutations, we train a domain-specialized generative model, LyraGen, with inherent semantic awareness to generate high-quality, semantically rich instruction sequences. Empirical results show Lyra achieves up to 1.27x higher coverage and accelerates end-to-end verification by up to 107x to 3343x compared to state-of-the-art software fuzzers, while consistently demonstrating lower convergence difficulty.

Transformer-based large language models are increasingly constrained by data movement as communication bandwidth drops sharply beyond the chip boundary. Wafer-scale integration using wafer-on-wafer hybrid bonding alleviates this limitation by providing ultra-high bandwidth between reticles on bonded wafers. In this paper, we investigate how the physical placement of reticles on wafers influences the achievable network topology and the resulting communication performance. Starting from a 2D mesh-like baseline, we propose four reticle placements (Aligned, Interleaved, Rotated, and Contoured) that improve throughput by up to 250%, reduce latency by up to 36%, and decrease energy per transmitted byte by up to 38%.

Macro placement is a critical stage in physical design, directly impacting the quality and performance of VLSI circuits. We propose a reinforcement learning (RL)-based macro placement framework that integrates proven design practices through a design-practice-embedded action mask, including peripheral placement, dead space avoidance, and proximal placement for macros with shared design hierarchy and physical footprint. Unlike previous RL based methods, our method uses macro clusters-formed according to design hierarchy and physical footprint-as the basic placement units, which reduces placement steps and consequently accelerates convergence and improves runtime. The proposed framework also introduces a novel compaction method to minimize wasted area caused by grid granularity, and jointly optimizes macro cluster location and tiling pattern for more effective exploration. Experimental results show that our approach achieves expert level placement quality and consistently outperforms three leading commercial macro placers on industrial designs, with reduced turnaround time. On public benchmarks, our method achieves up to 25.37% and 39.51% improvements in worst negative slack (WNS) and total negative slack (TNS), respectively, over five state of the art (SOTA) placers. These results demonstrate the effectiveness and real-world applicability of our RL based framework, paving the way for further advancements in physical design automation.

To deploy large Mixture-of-Experts (MoE) models cost-effectively, offloading-based single-GPU heterogeneous inference is crucial. While GPU–CPU architectures that offload cold experts are constrained by host memory bandwidth, emerging GPU-NDP architectures utilize DIMM-NDP to offload non-hot experts. However, non-hot experts are not a homogeneous memory-bound group: a significant subset of warm experts exists is severely penalized by high GPU I/O latency yet can saturate NDP compute throughput, exposing a critical compute gap. We present TriMoE, a novel GPU–CPU–NDP architecture that fills this gap by synergistically leveraging AMX-enabled CPU to precisely map hot, warm, and cold experts onto their optimal compute units. We further introduce a bottleneck-aware expert scheduling policy and a prediction-driven dynamic relayout/rebalancing scheme. Experiments demonstrate that TriMoE achieves up to 2.83$\times$ speedup over state-of-the-art solutions.

Differentiable techniques for timing optimization have be-come the dominant paradigm in global placement, surpassing weight-tuning heuristics by directly leveraging gradients that encompass full-chip context. However, in detailed placement, state-of-the-art flows still rely on rule-based or enumeration-centric methods that ignore existing gradient landscape, sacrificing significant wirelength only for marginal timing gains. To overcome this issue, we present LATTE, the first legality-assured, end-to-end differentiable timing-driven detailed placer that fuses contin-uous gradient smoothness with detailed discrete granularity. Particularly, at each iteration, LATTE relaxes local density constraints around selected timing-critical cells, steering relocation from exact timing and wirelength gradients with step sizes in annealed schedules, and enforces end-of-place legality via incremental legalization and bad-move filtering. Across input placements from mainstream commercial and academic placers, LATTE consistently delivers significant timing improvement with minimal routed wirelength impact while ensuring legal final solutions. On 15 designs in a 7nm technology node, LATTE on average improves state-of-the-art timing-driven detailed placers including DREAMPlace-4.0 TCAD and Rsyn by 29.7% in TNS and 44.4% in routed wirelength, with all metrics verified by an industry-leading commercial tool.

Recent progress in satellite formation flight in Low Earth Orbit (LEO) is driving demand for energy-efficient AI accelerators with strong soft-error resilience. This paper proposes a co-design of a fault-tolerant neural network and hardware that combines tolerance-aware temporal redundancy with sparse outer-product computation. A theoretical bound on single-bit-flip effects in residual-quantized dot products enables selective protection of only the most vulnerable computations. In addition, a zero-skip outer-product unit exploits activation sparsity created by residual quantization to reduce redundancy overhead. Implementation results show that the proposed design achieves a 16.0% speedup over the non-fault-tolerant model while keeping area overhead to 0.20–1.26%.

Chain-of-Thought (CoT) reasoning in large language models (LLMs) significantly improves accuracy on complex tasks, yet incurs excessive memory overhead due to the long think stage sequences stored in the Key-Value (KV) cache. Unlike traditional generation tasks where all tokens are uniformly important, CoT emphasizes the final answer, rendering conventional KV compression strategies ineffective. In this paper, we present Crystal-KV, an efficient KV cache management framework tailored for CoT reasoning. Our key insight is the answer-first principle. By mapping answer preferences into think-stage attention map, we distinguish between SlipKV, which mainly maintains the reasoning flow but may occasionally introduce misleading context, and CrystalKV, which truly contributes to the correctness of the final answer. Next, we propose an attention-based Least Recently Frequently Used algorithm. It precisely identifies when a SlipKV entry's utility expires and evicts it, retaining CrystalKV without disrupting reasoning flow. Finally, we introduce an adaptive cache budget allocation algorithm. Based on the dynamic proportion of CrystalKV, it estimates the importance of each layer/head and adjusts the KV cache budget during inference, amplifying critical components to improve budget utilization. Results show that Crystal-KV achieves state-of-the-art KV cache compression, significantly improves throughput, and enables faster response time, while maintaining, or even improving, answer accuracy for CoT reasoning.

In real-time systems, both individual task execution and data propagation must meet strict timing constraints. Cause–effect (CE) chains are widely used to analyze such behaviors by end-to-end latency. However, timing anomalies (TAs) can distort it, where a local reduction in execution times leads to an increase in the overall end-to-end latency. As a result, precisely analyzing the upper bounds of the latency becomes challenging, and such systems typically exhibit larger upper bounds than TA-eliminated systems. Existing studies either eliminate TAs by completely sacrificing average latency to simplify analysis or, despite adopting complex safe analysis methods, do not eliminate TAs effectively, still having high latencies. To address this issue, we identify two basic causes of TAs in end-to-end latency. Based on these causes, we propose the first treatment that eliminates TAs in the latency with negligible average latency loss using Deterministic Data Flow (DDF). We further formally prove its TA-free property. Therefore, we can get a precise upper bound for latency when all jobs execute with their worst-case execution times. Experimental results show that it effectively reduces the maximum end-to-end latency, the average latency, and latency jitter compared with the state-of-the-art (SOTA) method.

While chiplet-based 2.5D integration offers scalable high-performance computing with reduced manufacturing cost, it also poses significant challenges in design closure. Achieving timing closure in chiplet-based systems is notoriously difficult and frequently demands repeated engineering change orders (ECOs) and architectural-level iterations. To overcome these challenges, we propose ChiPlanner, a holistic {early-stage} design planner that integrates chiplet partitioning and physical planning. ChiPlanner first employs approximate placement to estimate post-chiplet-placement timing in advance of partitioning, which provides guidance for partitioning and helps reduce timing gaps. It further models inter-chiplet delay and incorporates a parallel net-weighting strategy in timing-driven physical planning to optimize overall system performance. Moreover, Bayesian optimization is leveraged to systematically explore the trade-off between chiplet manufacturing cost and system timing. Experimental results demonstrate that incorporating ChiPlanner's early-stage planning enables downstream chiplet design tools to achieve notably superior optimization outcomes, delivering average improvements of 42.4% in total negative slack (TNS) and 16.8% in worst negative slack (WNS). These results confirm that accurate early-stage planning provides a far better initialization for chiplet design and significantly reduces the burden on later ECOs and architectural-level iterations.

Speculative decoding enhances the inference efficiency of large language models (LLMs) by generating drafts using a small draft language model (DLM) and verifying them in batches with a large target language model (TLM). However, adaptive drafting inference on a mobile single-NPU-PIM system faces idle overhead in traditional operator-level synchronous execution and wasted computation in asynchronous execution due to fluctuations in draft length. This paper introduces AHASD, a task-level asynchronous mobile NPU-PIM heterogeneous architecture for speculative decoding. Notably, AHASD achieves parallel drafting on the PIM and verification on a single NPU through task-level DLM-TLM decoupling and specifically, it incorporates Entropy-History-Aware Drafting Control and Time-Aware Pre-Verification Control to dynamically manage adaptive drafting algorithm execution and pre-verification timing, suppressing invalid drafting based on low-confidence drafts. Additionally, AHASD integrates Attention Algorithm Units and Gated Task Scheduling Units within LPDDR5-PIM to enable attention link localization and sub-microsecond task switching on the PIM side. Experimental results for different LLMs and adaptive drafting algorithms show that AHASD achieves up to 4.2× in throughput and 5.6× in energy efficiency improvements over a GPU-only baseline, and 1.5× in throughput and 1.24× in energy efficiency gains over the state-of-the-art GPU+PIM baseline, with hardware overhead below 3% of the DRAM area.

The partitioned microarchitecture of Streaming Multiprocessor (SM) is a fundamental design that enables massive parallelism in modern General-Purpose Graphics Processing Units (GPGPUs). This approach, however, inherently introduces two critical inefficiencies: vast data redundancy across distributed private registers and severe conflicts and load imbalance in the limited banks. To holistically address these cross-partition bottlenecks, this paper introduces CODA, a cooperative Register File (RF) distribution and arbitration framework. CODA is composed of two synergistic mechanisms: the Cooperative Register Renaming (CRR), which eliminates data redundancy by maintaining a single physical copy of shared data across sub-cores, and the Dual-Skewed Arbitrator (DSA) that mitigates fine-grained bank conflicts by incorporating the operand collector ID into its arbitration logic. Evaluations on a diverse suite of deep learning workloads show that CODA exhibits superior performance compared to its baseline architecture, achieving a speedup of 28.9% alongside a 15.6% reduction in RF power consumption. These gains are directly attributed to a 15.9% reduction in RF load imbalance and a 12.7% lower bank conflict rate.

Programmable RISC-V soft cores are becoming more widespread in data-center scenarios, making it crucial to design efficient systems that deploy them on FPGA chips with HBM memory. Toki, released as open source, is the first hardware-software framework that enables profiling the performance of HBM on FPGA accelerator cards by jointly considering (i) the execution of workloads on RISC-V soft cores instantiated on the FPGA and (ii) the injection of memory traffic from the host system via DMA over PCIe, providing insights that cannot be obtained with synthetic traffic generators alone. Extensive experiments target an AMD Alveo U55C card, deploying up to 60 RISC-V compute cores and stressing its HBM2 memory through real-world applications and microbenchmarks with user-defined access patterns. Results showcase how Toki can effectively profile the impact on HBM performance of the compute cores' organization, the workload's memory access patterns, data locality, contention over the memory controllers, and host traffic.

Three-dimensional (3D) printing enables low-cost, rapid prototyping of complex microfluidic biochips, but light penetration during printing distorts small, multi-layered structures. Existing solutions are either inaccessible or overlook localized geometric effects, leading to inaccuracies that degrade device performance. We propose a novel physics-aware, data-driven design-for-manufacturing approach to improve dimensional fidelity. Using a new dataset of design-fabrication discrepancies, our machine learning-assisted method predicts spatially resolved compensation values. Experiments on complex multi-layer devices demonstrate that our method significantly enhances geometric accuracy and consistently outperforms existing compensation strategies, even with low-cost hobby-grade printers and off-the-shelf resins.

Co-designing chiplet-based neural-network accelerators spans partitioning, placement, dataflow, and microarchitecture under tight energy and latency limits. Fast system-level estimators scale to large searches but blur intra-core effects that dominate energy; fine-grain reference models capture them but are too slow in-loop. We close this speed–fidelity gap with a coarse-to-fine flow: a compact, architecture-aware surrogate of intra-core cost guides the global search, and only top designs are rechecked with the reference model. Our contributions are an energy-focused feature space and a lightweight predictor across convolutional and GEMM-like workloads. On ResNet-50 and a Transformer, we reduce a manufacturing-weighted energy–delay objective by up to 62\% and 44\%, respectively.

As large language models (LLMs) continue to scale in size and complexity, DRAM access has become a performance bottleneck, especially during the memory-bound decoding phase dominated by general matrix-vector multiplication (GEMV) operations. Recent work has explored near-/in-memory computing to address bandwidth limitations. Among these, Processing-Using-DRAM (PUD) offers a unique advantage as it performs logic operations entirely within DRAM peripherals with minimal circuit changes, enabling deployment on commercial off-the-shelf (COTS) DRAM. While prior work reported multi-input logic operations, its potential to accelerate GEMV operations in LLMs remains underexplored due to the limited compute capability of DRAM sense amplifiers (SAs). To overcome this challenge, we propose PAGE, a PUD architecture that accelerates GEMV through four key optimizations: (1) mat-level parallelism that exploits row-level parallelism by activating SAs across multiple mats; (2) inversion-enabled SA supporting NOT operations within a mat; (3) AP-based row copy mechanism that performs simultaneous source–destination activation with only control-signal changes; and (4) adaptive adder-tree accumulation that reduces accumulation cycles. We demonstrate the baseline PUD architecture on a COTS DRAM–FPGA platform to verify the functionality and timing of PUD operations, implement the modified circuits in TSMC 16nm for circuit-level evaluation, and build a in-house simulator for system-level throughput and energy analysis. Overall, PAGE achieves up to 14× and 3.1× end-to-end throughput and energy improvement for GEMV workloads over the SoTA PUD designs, demonstrating its feasibility for accelerating memory-bound LLM workloads with PUD.

Point-based neural networks have become the mainstream approaches for point cloud processing. However, they heavily rely on computationally intensive neighbor search operations like K-Nearest Neighbors (KNN) and ball query, which create significant bottlenecks for deployment in resource-constrained environments.In this paper, we present PS-CAM, a novel NOR-CAM-based accelerator designed to support both ball-query and KNN efficiently. PS-CAM converts the ball-query operation into a set of range search problems, formulating a one-shot search via the RENÉ range query scheme. To enhance energy efficiency within this scheme, a Two-Level Region-Partitioned (TLRP) technique is adopted, which reduces the number of activated CAM banks simultaneously. For KNN search, PS-CAM employs a progressive method through a series of ball-queries with increasing radius. The search iterations are bounded by the Density-Aware Radius Estimation (DARE) method, which rapidly approximates the KNN-equivalent ball radius (KEBR), thereby drastically reducing the need for repeated queries. Compared with prior works, PS-CAM demonstrates significant performance gains, achieving speedups of 1.25~1.33× and an energy efficiency improvement of 142× in ball query. For KNN task, PS-CAM delivers a speedup of 4.6~27.2× and energy-efficiency improvements of 7.1~2578×.

This work presents a silicon-verified analog–mixed-signal (AMS) layout-automation framework integrating a circuit-level analog standard-cell (CLAS) library with self-biasing circuits in a digital place-and-route (PnR) environment. Unlike transistor-level stem-cell approaches, the CLAS library standardizes matched circuit-level blocks, including self-biased amplifiers, current mirrors, and delay cells. Fabricated 180-nm and 65-nm CMOS chips validate fully automated, DRC/LVS-clean layouts for a current source, adaptive-bandwidth PLL, and probabilistic computer. All benchmarks show strong pre-/post-layout and silicon correlation, with the PLL exhibiting 0.98–1.50 ps simulated and 4.1 ps measured jitter. The framework achieves ≥96 % area utilization, 14.4–69.5 % DCAP density, and <1 min–1 hr runtime, demonstrating scalable, silicon-consistent AMS automation.

Register-transfer-level (RTL) simulation is commonly accelerated through multi-threading and event-driven technique. However, when these techniques are combined, severe load imbalance arises: in event-driven execution, circuit regions exhibit highly uneven activity, leaving many threads idle with very low utilization. Existing multi-threaded RTL partitioning models often optimize full-cycle execution and ignore the dynamic activity variation that dominates event-driven workloads. We present PGSIM, a multi-threaded event-driven RTL simulator that incorporates runtime activity information into its partitioning model. Our model augments hypergraph weights with measured activity frequency and inter-block activation correlation, which is efficiently estimated through a lightweight MinHash profiler. By aligning thread assignment with true activity patterns, PGSIM substantially reduces idle time and improves utilization. Across experiments on large benchmarks, PGSIM achieves 20–30% higher performance than its activity-unaware version, delivers a simulation speed of 200-400 kHz and up to 8.9× speedup over Verilator. These results demonstrate that runtime activity modeling is essential for scalable multi-threaded event-driven simulation.

Cache partitioning mechanisms improve system performance by judiciously adjusting cache space among applications. Its effectiveness can be enhanced by partitioning in both time and space. However, existing solutions are limited to only one dimension. This paper presents Cachence, a fine-grained cache partitioning mechanism in both time and space. Cachence profiles cache access patterns with theoretically guaranteed accuracy while incurring fixed storage overhead. Based on runtime microarchitectural statistics, we also propose a lightweight yet precise performance prediction model. Our evaluation shows that Cachence outperforms existing approaches by an average of 9.5% to 28.2%, and up to 48.8% on a 16-core system.

Hybrid Transactional and Analytical Processing (HTAP) workloads are widely deployed in production systems. Under HTAP workloads, frequent updates lengthen the version chains maintained in Multi-Version-Concurrency-Control (MVCC) systems. Longer version chains require Visible Version Searching (VVS) to scan more versions during analytical queries. In-Storage Computing (ISC) technique alleviates the I/O burden. We propose VALVE to offload the VVS process to a Computational-Storage-Device (CSD). VALVE first solves the consistency issue under host-CSD concurrency. A frugal skip list is introduced in VALVE to further accelerate the version-chain traversal. Experimental results show that VALVE reduces end-to-end scan latency and improves analytical throughput.

Disaggregated memory systems replicate data across memory nodes to ensure strong consistency and durability, but synchronous replication quickly saturates the compute node's RDMA NIC as the replica count grows. We propose GWrite, a hardware-oriented RDMA primitive, and GWrap, a co-designed replication protocol that offload replication fan-out to memory-side RNICs while preserving one-sided RDMA semantics. A software prototype that emulates GWrite on commodity RNICs achieves up to 2.18× higher throughput in a distributed transaction system and reduces replication-induced throughput degradation from 46.7% to 19.7% in a replicated hash table, showing that exploiting memory-side RNIC outbound capacity can substantially alleviate compute-side IOPS bottlenecks in write-intensive disaggregated deployments.

Analog circuits exhibit rich multi-terminal relationships that are poorly captured by conventional graph-based learning methods. We introduce \coin, a domain-aware foundation model that operates directly on a hypergraph representation tailored to transistor-level behavior. \coin integrates specialized transistor modeling, voltage-aware positional encoding derived from topological distances to VDD/VSS, and a transformer-enhanced hypergraph neural network to improve expressivity and structural discrimination. We evaluate \coin on circuit classification and specification regression. Experimental results show that \coin significantly outperforms both graph- and hypergraph-based baselines, proving the efficacy of our domain-aware approach.

Sparse Mixture-of-Experts (MoE) models offer a powerful way to increase the capacity of large language models without proportionally increasing computation. Yet, their extremely large expert weight parameters create severe memory challenges for consumer-grade GPUs and edge devices. Existing offloading and hybrid CPU–GPU approaches fall short in fully utilizing CPU resources, and their coarse-grained scheduling and poorly overlapped CPU-GPU data transfers leave CPU cores frequently idle, thus causing pipeline bubbles and exacerbating overall system inefficiency. We present MoE-Balance, a system that efficiently utilizes heterogeneous CPU-GPU resources for MoE inference. The key innovations include a fine-grained dynamic scheduler that distributes expert tasks based on real-time load, and a cross-layer prefetching and chunked transfer mechanism that overlaps computation with weight movement via PCIe. Experiments on Mixtral-8x7B show that MoE-Balance achieves 1.6x higher throughput and 37.5% lower end-to-end latency compared with state-of-the-art hybrid baselines, demonstrating strong performance gains under memory-constrained settings.

Modern vehicles integrate multiple in-vehicle networks (IVNs), such as Controller Area Network (CAN), Automotive Ethernet, and host systems, to support advanced automation and connectivity. While these networks enable new functionalities, they also expand attack surface across multiple domains. Sophisticated multi-stage attacks exploit these surfaces to propagate covertly and existing vehicular IDS systems cannot detect them as these attacks cause minor changes in IVNs. This paper presents SCIMI, a Semantic-aware Collaborative Intrusion detection system for Multi-domain In-vehicle networks, which learns inter-domain causal relationships to identify subtle, coordinated attacks that evade single domain intrusion detection systems. SCIMI aligns asynchronous traffic patterns through a dual window temporal model, extracts semantic features via domain adaptive encoders, and applies cross domain attention to correlate suspicious behaviors. A dataset is also released for collaborative IDS. Experiments show that SCIMI achieves over 99% F1-score with a 17% improvement over state-of-the-art methods, while maintaining low false positive alarms and real time inference efficiency, underscoring its applicability to real time automotive cyber-security.

The increasing size of large language models (LLMs) has led to a surge in memory requirements during training, often exceeding the capacity of high-bandwidth memory (HBM). Swap-based memory optimization incurs neither accuracy loss nor additional end-to-end overhead when effectively overlapped, thus being an attractive solution. However, existing swap methods assume consistent operator sequences, which is impractical in Eager Mode, where operator sequences can vary across iterations. We propose SmartSwap, which redesigns the end-to-end process of swap-based memory optimization and is the first work to consider varying operator sequences in Eager Mode. SmartSwap (i) introduces a lightweight online profiler to enable continuous profiling for monitoring operator sequences, (ii) generates effective swap policies with limited operator information, and (iii) optimizes the policy execution module for accurate policy application and better performance. Experimental results demonstrate that SmartSwap reduces profiling overhead by 84.25%, enables training models up to 4× larger than hardware memory while adapting to changes in operator sequences, improves performance by up to 38.94% compared to recomputation or high-degree parallelism.

Substantial weight and KV cache transfers between the GPU and HBM severely constrain Large Language Model (LLM) inference system performance. While LLM compression techniques can reduce memory footprint and transfer volume, existing methods are often task-specific and compromise model accuracy. This work proposes a mega-buffer architecture (MBA) that integrates gigabyte-scale on-chip buffers utilizing the embedded DRAM (eDRAM) technology recently introduced by TSMC. To fully leverage this large on-chip memory, we introduce a KV cache prioritized mapping (KVP) scheme that minimizes inefficient KV cache traffic between the HBM and the chip. Furthermore, a highly efficient pipeline integrating double buffering mechanism (DB) is co-designed with an iteration-aware eviction strategy (IA) to enhance data reuse and sustain high compute utilization. Evaluation results show that MBA attains 5.99x and 3.63x end-to-end speedup, and 8.86x and 4.93x energy efficiency improvement against GPU and LLM accelerator baselines, demonstrating a highly efficient architectural solution for LLM inference.

Distributed large language model (LLM) training faces prevalent failures and requires efficient checkpointing. State-of-the-art approaches employ partition-based pipelined checkpointing, splitting checkpoints into partitions for concurrent processing. However, existing solutions rely on a fixed partition size, which our analysis reveals is suboptimal for LLM training: large partitions cause bandwidth stalls during forward passes, while small partitions incur substantial startup overhead during backward passes. We propose AsymCheck, which employs asymmetric partitioning: small partitions for forward passes and large partitions for backward passes, plus selective partition compression and batched flushing optimizations. Evaluation on 64 GPUs shows AsymCheck reduces training time by 20.1%-48.2% over state-of-the-art methods, approaching no-checkpointing efficiency.

Peripheral Component Interconnect Express (PCIe) is the de facto interconnect standard for high-speed peripherals and CPUs. The development of PCIe devices for emerging applications requires realistic Transaction Layer Packet (TLP) traces that accurately simulate device-CPU interactions. While generative AI offers a promising avenue for synthesizing complex TLP sequences, it is prone to a critical challenge inherent in all generation tasks: hallucination. Naively applying these models often produces traces that violate fundamental PCIe protocol rules, such as ordering and causality, rendering them unusable for device simulation. To resolve this, our work introduces a methodology to bridge the gap between generative AI and high-fidelity device simulation. This paper presents Phantom, a framework that systematically addresses AI-generated hallucinations in TLP synthesis. Phantom achieves this by coupling a generative backbone with a novel post-processing filter that enforces PCIe-specific constraints, effectively eliminating invalid TLP sequences. We validate Phantom's effectiveness by synthesizing TLP traces for an actual PCIe network interface card. Experimental results show that Phantom produces practical, large-scale TLP traces, significantly outperforming existing models, with improvements of up to 1000$\times$ in task-specific metrics and up to 2.19$\times$ in Fréchet Inception Distance (FID) compared to backbone-only methods. The prototype implementation has been made open-source.

Face-to-Face 3D ICs enable advanced vertical integration but pose critical challenges for clock tree synthesis (CTS). Existing pseudo-3D flows rigidly partition clock paths across dies, fragmenting common paths and crippling Common Path Pessimism Removal (CPPR), resulting in excessive skew and inefficient hybrid bonding terminal (HBT) utilization. We present FlexiCTS, a correct-by-construction CPPR-aware framework featuring adaptive cross-die buffer assignment to maximize path sharing and optimize HBT allocation. Experimental results show that FlexiCTS achieves 4.1$\times$ skew reduction and 88\% fewer HBTs than state-of-the-art methods, while simultaneously matching 2D timing quality with superior resource efficiency.

Superconductor electronics have increasingly shifted away from RSFQ and its variants toward logic families that eliminate explicit gate-level clocking. While this transition enables simpler circuits and more efficient architectures, it also introduces an implicit reliance on dual-rail codes, resulting in inherent gate duplication. This work presents a duplication-aware retiming methodology for Josephson junction (JJ) count minimization, co-optimizing register placement and polarity assignment. The approach applies beyond SFQ to any monotonic circuit. We further identify cell interfaces—specifically, interconnect drivers, receivers, and fanout (FO) elements—as dominant contributors to JJ count in each cell. A new amplifier design is introduced to reduce these costs, integrated within existing SFQ cells, experimentally verified, and characterized to form a new SFQ cell library. Our results demonstrate a 63-71% JJ count reduction in single-cycle implementations and 41-66% reduction in multi-cycle implementations compared to the prior state-of-the-art. The latter establishes a new Pareto frontier, achieving both shorter critical paths and lower JJ counts than the best-to-date single-cycle implementations.

The IC3/PDR algorithm is a cornerstone of hardware model checking, and machine learning (ML) has been explored to guide its critical inductive generalization step. However, prior ML methods are built upon a per-clause graph analysis paradigm, requiring repetitive and costly graph processing for every clause, creating a severe scalability bottleneck. Therefore, we introduce LeGend, a framework that completely replaces this paradigm with one-time global representation learning. LeGend architects a domain-adapted self-supervised learning task to generate latch embeddings that encode global circuit properties. These pre-computed embeddings enable a lightweight model to predict high-quality lemmas with negligible overhead, effectively decoupling expensive learning from fast inference. Experiments show our approach accelerates two state-of-the-art IC3/PDR engines across a diverse set of benchmarks, presenting a promising path to scale up formal verification.

A transaction ensures an all-or-nothing guarantee for a set of read/write operations. While modern transaction processing systems provide atomicity and consistency for data center applications, their performance is fundamentally limited by a critical memory bandwidth bottleneck, caused by massive numbers of read/write operations. Processing-in-memory (PIM) architectures offer a promising solution with their high aggregate bandwidth. However, directly applying PIM becomes inefficient in practice due to load imbalance and costly data transfers among PIM processors. To bridge the gap between transaction processing and PIM architectures, this paper presents Onyx, a high-throughput transaction processing system that efficiently executes transactions on a real UPMEM PIM prototype. To fully leverage the high parallelism and bandwidth of PIM, Onyx orchestrates the transaction execution workflow to maximize local accesses while maintaining load balance across PIM processors. It further employs rank-level asynchronous data transfer to reduce communication overhead. Extensive evaluation using real-world YCSB and TPC-C benchmarks shows that Onyx significantly outperforms state-of-the-art transaction processing systems.

Technology mapping is a critical yet challenging stage in logic synthesis. While Large Language Models (LLMs) have been applied to generate optimization scripts, their potential for core algorithm enhancement remains untapped. We introduce MappingEvolve, an open-source framework that pioneers the use of LLMs to directly evolve technology mapping code. Our method abstracts the mapping process into distinct optimization operators and employs a hierarchical agent-based architecture, comprising a Planner, Evolver, and Evaluator, to guide the evolutionary search. This structured approach enables strategic and effective code modifications. Experiments show our method significantly outperforms direct evolution and strong baselines, achieving 10.04\% area reduction versus ABC and 7.93\% versus mockturtle, with 46.6\%--96.0\% $S_{overall}$ improvement on EPFL benchmarks, while explicitly navigating the area--delay trade-off. We have open-sourced our framework to foster reproducibility and further research.

In Large Language Model (LLM) inference services, it is challenging to make a parallelism strategy configuration, to efficiently process the requests of variance context lengths. Requests of long context require high degree of parallelism to provide more memory for Key-Value (KV) Cache, while requests of short context prefer low degree of parallelism to increase concurrency, thus improving throughput. To maintain high throughput while supporting large context lengths on demand, we propose Amoeba, a runtime Tensor Parallel (TP) transformation for online LLM inference services, which adaptively adjusts the TP of running instances to align with the dynamics of incoming requests. Evaluations using real-world traces show that Amoeba improves throughput by 1.75×-6.57× compared to state-of-the-art solutions.

DRAM-based processing-in-memory (PIM) emerged as a promising approach to alleviate the memory wall by executing massively parallel bitwise operations inside DRAM arrays. However, most prior designs operate on a single bitline and leave the dual-rail complementary signals naturally available on each bitline pair underutilized. We present DRCA, a novel dual-rail compute-and-access scheme that exploits both rails of a bitline pair for computation and data access. DRCA integrates two dual-contact compute cells, DRCA-OR and DRCA-XOR, which leverage full-swing dual-rail signaling on the bitline pair to perform bitwise logic with high reliability. Furthermore, the design enables concurrent operations on a single bitline pair, improving the efficiency of complex bitwise logic processing. Our evaluation shows that DRCA reduces failure rate by 2.29x compared with the most robust prior PIM design, while delivering superior average performance on basic bitwise operations.

In advanced process nodes, the pursuit of extreme PPA optimization has driven an explosion in the demand for customized standard cells. To satisfy this demand, automated layout synthesis has been increasingly adopted to explore vast design spaces. However, this paradigm shifts the bottleneck from design creation to verification, as characterizing the massive volume of generated variants via SPICE is computationally prohibitive. Meanwhile, conventional geometric heuristics fail to proxy PPA at advanced nodes due to dominant layout effects. Existing learning-based surrogates often lack the fidelity to capture these complex dependencies. To bridge this gap, we propose EPiCell, an electro-physical co-modeling framework for rapid PPA estimation. EPiCell features a Heterogeneous Graph Transformer (HGT) that explicitly models transistors, routing metals, and supply rails as distinct entities, unifying circuit topology with fine-grained layout geometry. By employing relation-aware attention, it effectively captures the non-local electro-physical interactions governing cell performance. Validated on a dataset of over 18,000 auto-generated layouts based on ASAP7, EPiCell achieves high fidelity against SPICE simulations, with low average prediction errors of 1.82% for leakage power, 4.01% for internal power, 3.06% for delay, and 3.29% for transition. Crucially, it demonstrates superior ranking consistency with SPICE, attaining a median Spearman Rank Correlation Coefficient of 0.90 for internal power, 0.81 for delay, and 0.70 for transition. This offers a scalable surrogate model to enable efficient design space exploration.

Matrix extensions are essential in modern CPUs, but existing implementations with tight pipeline coupling and fine-grained synchronous instructions hinder integration and high-performance kernel implementation. We propose an adaptable matrix extension that carefully decouples matrix-unit from the CPU pipeline for low-overhead integration, unified software support, and reuse of existing compute and memory resources. It supports asynchronous operations and enables efficient matrix–vector overlap. Integrated into four open-source RTL CPUs, the design achieves over 90% utilization and up to 2.31× speedup on ResNet50, BERT, and Llama3 over Intel AMX, with 30% gains from matrix–vector overlap, while a 4TFLOPS@14nm implementation occupies 0.53mm².

Machine learning can reduce 3D-ICs thermal analysis runtime from hours to seconds, yet most existing ML-based thermal models train each chip independently from scratch, demanding large datasets while failing to exploit the mathematical equivalence between heat conduction and diffusion-type PDEs. We demonstrate that foundation neural operators pretrained on diverse PDE families enable effective transfer to 3D-IC thermal simulation. Building on this insight, we develop PNO-Therm, a specialized model obtained through targeted fine-tuning, which surpasses the previous state-of-the-art method using less than 20% of the training data. At equal dataset sizes, our method achieves 6–10× lower MAE, 3.5× reduced GPU memory consumption, and over 3× faster training while maintaining approximately 940× speedup versus FEM solvers. Validated across three representative 3D-IC designs, PNO-Therm establishes that pretrained neural operators provide a scalable pathway for high-accuracy thermal modeling under limited data.

Optimizing CUDA kernels is a challenging and labor-intensive task, given the need for hardware-software co-design expertise and the proprietary nature of high-performance kernel libraries. While recent large language models (LLMs) combined with evolutionary algorithms show promise in automatic kernel optimization, existing approaches often fall short in performance due to their suboptimal agent designs and mismatched evolution representations. This work identifies these mismatches and proposes cuPilot, a strategy-coordinated multi-agent framework that introduces strategy as an intermediate semantic representation for kernel evolution. Key contributions include a strategy-coordinated evolution algorithm, roofline-guided prompting, and strategy-level population initialization. Experimental results show that the generated kernels by cuPilot achieve an average speed up of 3.09$\times$ over PyTorch on a benchmark of 100 kernels. On the GEMM tasks, cuPilot showcases sophisticated optimizations and achieves high utilization of critical hardware units. The generated kernels are open-sourced at https://anonymous.4open.science/r/cuPilot-Kernels-1656.

Privacy-preserving machine learning via Fully Homomorphic Encryption (FHE) offers strong data confidentiality guarantees but suffers from prohibitive computational overhead. In this work, we improve the performance of private inference via fully homomorphic encryption on multi‑GPU environments. We achieve this through three key innovations: (1) an optimized tensor‑level FHE library based on the CKKS scheme that fuses low‑level encrypted primitives into high‑throughput GPU kernels, (2) an adaptive memory manager that dynamically orchestrates encrypted‑tensor placement to control peak memory usage, and (3) a multi‑GPU execution engine that partitions and balances workloads across devices to maximize utilization under constrained memory budgets. We evaluate our method on representative encrypted‑ML benchmarks and compare against state‑of‑the‑art CPU- and GPU‑based FHE systems, showing comparable single-GPU results since no existing work provides a multi-GPU implementation. Our eight-GPU configuration achieves strong scaling of 7.14x over the single-GPU execution, which in turn yields a 9.7x end-to-end cumulative improvement over the best prior work. We additionally implement all fused tensor-level operators within a full ResNet-20 inference pipeline on CIFAR-10, demonstrating that the method generalizes beyond MNIST-scale workloads. Results show efficient parallel scaling, with 8-GPU execution on ResNet-20 reaching 7.1x speedup over the state of the art under realistic memory constraints.

Estimating the true hardware cost of quantum machine learning (QML) models is challenging due to repeated circuit evaluations affected by noise, decoherence, and routing delays. Conventional metrics like gate count overlook such hardware-dependent effects. We propose an analytical quantum cost model that estimates required quantum hardware resources using real device calibration data, incorporating gate durations, routing overheads, and noise-induced inefficiencies. Complementing this, a classical cost model converts FLOPs into equivalent units, providing a unified hardware-aware hybrid cost metric. Integrating both, we then propose Hyb-HANAS framework which employs multi-objective NAS (NSGA-II) to jointly optimize accuracy, execution time, and parameter count in hybrid quantum–classical networks.

The rapid evolution of graph neural networks (GNNs) has introduced diverse computational patterns beyond the message-passing paradigm. To support end-to-end inference, existing accelerators need to integrate heterogeneous, loosely-coupled components, incurring significant inter-accelerator communication and low performance density. This paper introduces Florella, an acceleration framework for unifying inconsistent computational patterns in end-to-end GNN inference. We first propose the sliding reduction convention, a declarative language that provides a flexible and hardware-friendly representation for diverse GNN operations. Building upon this, we design a versatile architecture that enables atomic mapping of macro-operations. This architecture is centered around a novel Jacobian-logarithm unit, which enables high hardware reuse across operators by leveraging logarithmic transformation and approximation. Evaluated across a range of GNN models, Florella achieves an average speedup of 2.2x and reduces memory traffic by 2x compared to four state-of-the-art accelerators, while improving performance density by 3.3x.

Flash-based SSDs are prone to bit errors in flash cells. To ensure reliability, SSDs employ error correction codes (ECCs) that encode user data bits into codewords composed of data and redundant parity bits, enabling correction of a limited number of bit errors. In practice, however, the raw bit error rate (RBER) of SSDs fluctuates over time. We observe that for ECCs with a fixed code rate (the fraction of user data bits per codeword), longer codewords provide higher reliability, while shorter codewords offer lower read latency. To this end, we propose COLA, an adaptive coding framework that optimizes the code length (i.e., total number of user data and parity bits per codeword) for individual SSD pages to achieve low-latency reads while maintaining reliability guarantees and constant storage overhead. COLA adopts a failure-aware read mechanism that selectively transfers and decodes failed codewords, and integrates a failure-aware read-latency model to determine actual read operations based on current RBERs and select the optimal code length for each write operation. Evaluation using the MQSim simulation shows that COLA significantly reduces average and tail read latencies compared to the default fixed-code-length approach.

A hybrid Solid-State Drives (SSDs) integrates different modes of flash cells (e.g., single-level cell (SLC) and Quad-Level Cell (QLC)) and enables them to convert between each other, achieving both high performance and storage capacity. However, this hybrid design introduces a significantly larger design space than traditional SSDs with additional design factors such as flash conversion and data migration across different flash modes, leading to higher optimization complexity. Efficient management of such complexity requires deep hybrid SSD knowledge and dynamic adjustment mechanisms. Large language models (LLMs) offer a promising solution through their contextual reasoning and adaptive coordination capabilities. In this work, we explore the potential of using LLMs in understanding and efficiently managing hybrid SSD design space. We find that leveraging LLMs for knowledge-guided optimization of management parameters enables substantial performance gains. Building on these insights, we propose LLM-hybridSSD, an integrated optimization framework that formulates hybrid SSD management as a parameter-tuning problem, employs an LLM-based tuner for adaptive configuration, and applies reinforcement learning-based fine-tuning to align local lightweight models with domain-specific knowledge. Experimental results show an average 58.92% increase in throughput and a 28.56% reduction in write amplification (WA) compared with state-of-the-art schemes under different real-world workloads.

The increasing complexity of embedded software has made comprehensive manual testing impractical, motivating the use of automated techniques such as fuzzing. Coverage-guided fuzzers like AFL++ have shown strong results for conventional software but remain challenging to apply effectively in embedded contexts, where peripheral behaviors play critical roles. Existing approaches either use fast user-mode simulators, sacrificing peripheral realism, or rely on full-system simulators with manual instrumentation, limiting applicability to large-scale software. In this work, we present a novel framework that integrates AFL++ with a stateful SystemC-TLM virtual prototype to enable realistic fuzzing of embedded software. Fuzzer-generated inputs are injected directly into peripheral models, allowing peripherals to trigger natural side effects such as interrupts and FIFO updates. By integrating fuzzing with full-system simulation, our framework advances the effectiveness of pre-silicon testing for embedded systems. Results on embedded workloads show that our approach eliminates false positives while maintaining comparable code coverage and execution performance as state-of-the-art tools.

Deploying large language models (LLMs) on edge devices is critical for user privacy and low-latency inference. However, existing matrix-centric LLM accelerators suffer from limited throughput when handling fragmented non-linear operators due to tight edge-side resource constraints, and the absence of a general fusion mechanism frequently results in severe PE array underutilization during non-linear execution phases. To address these challenges, we propose UniNL, a unified execution framework designed to efficiently handle non-linear operators in LLMs. First, we introduce an abstraction model that decomposes non-linear operators into a sequence of primitives, leveraging polynomial approximation to enable point-wise operations to be executed on the PE array. Second, we implement lightweight microarchitectural extensions to the accelerator to efficiently support these primitives. Finally, we devise a primitive-aware fusion mechanism that effectively hides non-linear latency behind matrix operations. Experimental results demonstrate that UniNL achieves a 6.89× speedup and 7.26× energy-efficiency improvement on average compared to a Jetson AGX Orin baseline. Furthermore, UniNL outperforms state-of-the-art designs by 1.46× and 1.35× in average performance, respectively.

This paper presents AttestLLM, the first attestation framework to protect device vendors' hardware-level intellectual property by ensuring that only authorized large language models (LLMs) can execute on target platforms. To overcome the scalability and efficiency limitations of prior work, AttestLLM leverages an algorithm/software/hardware co-design approach to embed robust watermarks onto the activation of LLM layers. In addition, it optimizes the attestation protocol within the trusted execution environment, providing efficient ownership verification without compromising inference throughput. Evaluations on various on-device LLMs demonstrate AttestLLM's attestation reliability, fidelity preservation, and efficiency. Furthermore, AttestLLM exhibits resilience against forgery, replacement, and system attacks.

Mixture-of-Agents (MoA) is a widely adopted multi-agent paradigm, but existing MoA systems face two major challenges: excessive agent-to-agent connectivity and poor hardware efficiency. To address these two issues, we propose Faster-MoA, a unified algorithm-system co-design for efficient MoA serving. Faster-MoA has three innovations. First, we replace the conventional all-to-all topology with a hierarchical tree structure that introduces structured sparsity in agent connections. Second, we develop a run-time dynamic agent early-exit mechanism that prunes unnecessary agent connections basing on output semantic similarity and answer confidence. Third, we propose an agent-dependency-aware incremental prefilling mechanism that overlaps prefilling and decoding among agents with data dependencies to reduce inference latency. Together, these three innovations enable Faster-MoA to reduce end-to-end serving latency by up to 90% while achieving similar (only ±1% variation) or even higher task accuracy compared with MoA baselines using all-to-all agent connection.

Modern LLMs use diverse integer, floating-point, and microscaling (MX) precisions, but most accelerators are optimized for only a few formats. We propose AMBER, a general-purpose LLM accelerator for plug-and-play multi-precision deployment and compression of weights and KV caches in cloud and edge. AMBER introduces bit-transposed encoding that exploits bit-level statistical concentration for lossless compression across all of INT, FP, and MX formats. A precision-agnostic, stage-pipelined bit-serial PE further reuses bit-level redundancy for efficient versatile precision computation. Evaluated on 8 LLMs and 10 formats, AMBER boosts memory efficiency 1.17× and compute 3.16×, surpassing Olive and Tender in throughput and energy.

Task-oriented object detection on CLIP enables open-vocabulary, prompt-driven semantics but dense alignment and memory traffic block real-time edge use. We propose TorR, a brain-inspired algorithm–architecture co-design that replaces CLIP-style dense matching with hyperdimensional associative reasoning and exploits temporal coherence. TorR combines HDC similarity, graph reasoning with query caching and delta updates, and a lane-scalable, precision-gated item memory with RT-30/RT-60 control. A 28 nm TorR accelerator delivers real-time detection with millijoule energy and competitive AP at orders-of-magnitude lower energy.

Fill insertion need to consider not only density uniformity but also delay. Existing algorithms reduce such delay implicitly by minimizing proxies (fill amounts, overlays between fills, etc) but there remains misalignment between the reduction of proxies and improvement of the signal delay. We propose DiffFill, a novel differentiable framework for fill insertion that explicitly optimizes both uniformity and delay. At the heart of DiffFill is the CapFormer, a Transformer-based capacitance extractor that estimates capacitance values used to construct a differentiable delay objective based on the Elmore delay formulation. DiffFill significantly outperforms the state-of-the-art methods.

In integrated circuit manufacturing, the detection of nanoscale wafer defects is critical for yield improvement and root-cause analysis. However, scanning electron microscopy (SEM) defect datasets in modern production lines are typically long-tailed, with pronounced intra-class diversity and subtle inter-class differences. Most existing methods do not take these properties into account, leading to low recall on tail defects and frequent confusion between categories. To address this, we propose DiffTail, a framework that combines mask-guided diffusion with process-aware metric optimization. The mask-guided diffusion uses defect masks together with SEM-specific prompts that encode defect knowledge to synthesize tail defects at specified locations and of specified types, while latent-space fusion with normal SEM images preserves process-consistent background textures. The process-aware metric optimization module groups class prototypes based on image features that are correlated with process steps. It then applies inter-cluster separation and margin-based constraints to easily confused class pairs, making visually similar defects easier to distinguish. Extensive experiments show that DiffTail improves tail-class detection and segmentation over state-of-the-art methods. To facilitate reproducibility, a subset of the data is available at \url{https://anonymous.4open.science/r/Dataset-107B}, and the full dataset will be released upon acceptance.

Modern Non-Uniform Memory Access (NUMA) servers equipped with distributed Non-Volatile Memory Express (NVMe) storage present new challenges for I/O coordination. First, conventional page cache allocators ignore storage topology, resulting in inefficient cross-node cache placement and performance issues. Second, CPU schedulers overlook cache and storage locality, causing frequent cross-node cache accesses and further degrading performance. Third, the OS page cache employs a rigid eviction policy that fails to adapt to diverse application workloads, while even programmable alternatives often require complex manual tuning. To address these challenges, we propose Laelaps, a workload-aware I/O coordination framework for NUMA storage systems. Laelaps introduces three key techniques: (1) storage-topology-aware page cache placement, co-locating cache pages with their backing NVMe devices; (2) storage-topology-aware I/O thread scheduling that aligns thread placement with cache distribution to minimize cross-node accesses; and (3) workload-aware adaptive page caching that automatically selects eviction policies based on observed application access patterns. Evaluation shows that Laelaps achieves 1.41× geometric mean throughput improvement with 3.5% runtime overhead.

For the first time, this paper introduces an adaptive sparsely-gated mixture of experts neural network (ASG-MOENN) as a novel digital predistortion (DPD) framework for wide dynamic power range quadrature switched-capacitor power amplifiers (SCPAs). State-of-the-art (SOTA) DPD models suffer from fixed, high computational complexity, leading to inefficiency at lower power levels. To overcome this limitation, the proposed ASG-MOENN employs a dual-stage adaptive mechanism. First, it embeds the underlying physical principles of SCPA power variation to condition the input signal. Second, it incorporates an adaptive sparse gating mechanism that dynamically determines both which experts to activate and how many are required based on a cumulative confidence criterion, allowing the model to flexibly scale its run-time complexity according to the PA's operating state. Experimental results demonstrate that, compared with the SOTA baseline, the proposed model achieves superior linearization performance while reducing the average computational load by up to 50% across a 30-dB dynamic power range.

Multimodal stacks mixing ViTs, CNNs, GNNs, and transformer NLP strain embedded platforms due to heterogeneous compute and tight real-time constraints. We present TRINE, a single-bitstream FPGA accelerator and compiler that runs end-to-end multimodal inference without reconfiguration. It unifies layers as DDMM/SDDMM/SpMM on a mode-switchable PE array supporting weight/output-stationary systolic, 1×CS SIMD, and a routable adder tree with in-stream top-k token pruning. Dependency-aware layer offloading overlaps independent kernels across RPUs. On Alveo U50 and ZCU104, TRINE achieves up to 22.57× and 6.86× lower latency than RTX 4090 and Jetson Orin Nano at 20–21 W, with <2.5% accuracy loss and state-of-the-art efficiency.

Emulation-based dynamic analysis detects malicious software by observing runtime behavior in a controlled environment. Malware increasingly adopts evasion techniques to recognize such environments and hide malicious activities. In this paper, we propose EmuDRop, a minimalistic emulation-detection attack that exploits Intel reserved opcodes. EmuDRop leverages microarchitectural differences between real hardware and emulators to identify emulated execution. We reverse-engineer reserved opcodes, characterize their microarchitectural effects, and evaluate EmuDRop on five Intel CPU cores and QEMU, a widely used and representative emulator. The results show that EmuDRop reliably identifies emulated environments.

Video LLMs have achieved remarkable performance in processing hour-long videos, yet they suffer from severe memory overhead and latency due to expanding KV caches—critical bottlenecks for real-world online applications. To tackle this, LiveVLM is proposed: a training-free, query-agnostic framework featuring two key mechanisms. The Vision Sink Bucketing (VSB) processes video streams in real time, retains long-term details, and eliminates redundant KVs, while the Position-agnostic KV Retrieval (PaR) decouples positional embeddings to reduce irrelevant context interference via efficient page-level retrieval. Extensive experiments confirm LiveVLM delivers state-of-the-art accuracy on LLaVA-OneVision, outperforming both training-free query-agnostic methods and training-based online models.

Chain-of-thought (CoT) prompting enhances LLM reasoning by decomposing tasks into intermediate steps, but it increases decoding latency and memory usage. Mixture-of-Experts (MoE) models improve scalability via sparse expert activation, yet expert weights often exceed GPU capacity. Existing runtimes treat tokens uniformly, missing structural regularities where consecutive reasoning stages exhibit coherent expert activation patterns. This causes inefficient expert caching and excessive GPU-CPU data movement. We present SAEM, a stage-aware inference runtime that detects reasoning stage boundaries and exploits stage-level coherence in expert activation. SAEM applies stage-aware caching for GPU-CPU placement, combining token packing with in-situ CPU execution. SAEM achieves 1.54× speedup over state-of-the-art baselines under memory constraints.

DRAM scaling increases vulnerability to peripheral faults, making symbol level ECCs essential. LPDDR6 introduces a 12-bit data beat that misaligns with Reed Solomon codes with 8 or 16-bit symbol. An 8-bit RS code meets on-die parity budgets but cannot guarantee correction. A 12-bit RS code guarantees correction but exceeds the budget. CLUE-ECC pools the 16-bit on-die and the system ECC parity for proper correction with less parity. Evaluation shows superior error handling with 33.3% on-die parity storage, 14.83% area and 24.18% power savings with the same bandwidth impact compared to a conventional RS code.

Video diffusion transformers (vDiTs) generate high quality but pay quadratic self-attention cost, making inference prohibitive at video-token scales. The challenge is input-adaptive sparsity: selecting critical Q/K/V tokens with negligible overhead and executing them for end-to-end gains. We present \textsc{SPADE}, a training-free sparse-attention engine of three parts: (i) \textsc{vDiT-SSR}, specification defining 3D blocking candidates and formalizing dynamic masks via \emph{Summarizer}/\emph{Estimator} expressions; (ii) runtime \textsc{scheme generation} using SICS and a head-wise policy; and (iii) an executor with low-overhead index search, flash block-sparse attention, and kernel grouping. Across Hunyuan-Video, Wan~2.1/2.2, \textsc{SPADE} raises sparsity and speed and preserves quality, accelerating attention $2.26{\times}$--$3.40{\times}$ and end-to-end $1.49{\times}$--$1.80{\times}$.

KASLR is a critical defense on macOS, whose implementation on M-series silicon and the latest macOS is further strengthened by hardware–software mitigations, with no practical bypass. We perform a systematic reverse-engineering of the TLB on M-series silicon and uncover a novel user–kernel TLB side-channel, TLBarge, that enables precise monitoring of kernel instruction execution. Leveraging TLBarge, we demonstrate MistleTunnel, the first attack that compromises macOS 26's 15-bit KASLR by recovering its lower 8 bits. Operating solely through normal syscalls, MistleTunnel collapses the effective KASLR entropy to 0.39%, significantly reducing its intended security.

LLM inference stresses GPU memory with large model weights and KV caches, which requires efficient compression techniques. But existing approaches either sacrifice accuracy (e.g., quantization) or apply serial entropy coding (e.g., DFloat11) that limits throughput. Both constrain the overall inference efficiency. In this work, we propose ZipFloat, an LLM-oriented floating-point compressor that achieves massively parallel com-/decom-pression while preserving full precision. We observe that weights and KV-cache values in LLMs exhibit strong statistical redundancies, yet existing floating-point formats mask this redundancy and hinder effective compression. To address this, ZipFloat employs (1) Exponent Sparsification, which redefines the binary representation of floating-points to restore compressibility, and (2) Bit-Matrix Packing, which leverages this restored structure with GPU-native parallelism to deliver extreme throughput. Evaluations show that ZipFloat delivers up to 700 GB/s com-/decom-pression throughput, outperforming SOTA methods (e.g., DFloat11) by several orders of magnitude while maintaining comparable compression ratios, thereby reducing over 95\% TTFT and improving over 4x inference throughput in LLM systems.

While microarchitectural exploration for well-established processors relies on cycle-accurate simulators (CAS) for accurate evaluation, exploring without knowing both a microarchitectural optimization's capability to eliminate critical-path latency and its theoretical upper bound often leads to blind iteration. To address this, we propose IdealSim, an efficient and general simulation framework for constructing ideal scenarios on CAS, enabling early-stage identification of promising designs. Applied to the RTL-validated CAS of the XiangShan processor to explore the ideal critical-path value predictor, IdealSim achieves 7.93% higher modeling accuracy than prior work and shows that the critical-path value predictor can deliver an average performance gain of 5.61% (and up to 37.92%) in ideal scenarios. Our results provide an accurate performance upper bound, guiding subsequent microarchitectural trade-offs and optimization of the XiangShan processor.

Post-layout optimization is a critical step in modern chip design. However, existing Machine Learning (ML)-assisted methods struggle to capture the cross-stage reasoning dependencies that underlie the optimization challenges. While large language models (LLMs) excel at semantic reasoning, the lack of structural and physical awareness limits their effectiveness in post-layout optimization. To address these limitations, we propose DiffDEG, a diffusion-enhanced, reasoning-aware foundation model that bridges LLM-based semantic reasoning with circuit-level structural and physical representations. DiffDEG reformulates the conventional timing graph into a Design Evolution Graph (DEG), enabling cross-stage reasoning through text-annotated netlists. By leveraging directional diffusion and self-supervised pretraining, DiffDEG jointly interprets semantic, timing, and physical information, forming a unified representation adaptable to diverse optimization tasks. Experimental results show that DiffDEG consistently enhances optimization outcomes across multiple optimization paradigms, achieving an average 12.5% performance improvement and 4x runtime speedup over commercial tools.

General Matrix Multiplication (GEMM) is a fundamental kernel in scientific computing and deep learning and often dominates both performance and energy consumption, particularly in edge deployments with strict power and resource constraints. AMD's Versal ACAP offers heterogeneous components (AIEs, PL, PS) that can address these challenges, but identifying efficient mappings across these units is challenging, with prior work largely overlooking power-performance trade-offs. We introduce MALIWAN, an automated framework that generates Pareto-optimal GEMM mappings on Versal ACAP devices. MALIWAN combines fast analytical-model–based sampling with data-driven ML, using on-board measurements to train a surrogate that drives large-scale Design Space Exploration. Based on a collection of ≈6,000 on-board experiments, we first provide a comprehensive analysis of how different mapping configurations affect performance and power. We then evaluate MALIWAN on the Versal VCK190, demonstrating geomean improvements of 1.23× (up to 2.5×) in throughput and 1.25× (up to 2.7×) in energy efficiency over state-of-the-art works. Compared to NVIDIA GPUs, MALIWAN achieves up to 2.5× energy efficiency

The zone interface has emerged as a promising standard in consumer devices to support high random read performance, as its design reduces read amplification and enables efficient read parallelism. However, to support the underlying zone interface, the kernel's I/O subsystem must enforce strictly sequential writes per zone by logically ordering requests, which results in reduced write parallelism at the kernel level. Although prior work mitigates this by offloading the request reordering process to the on-device write buffer, the limited buffer size in consumer devices cannot accommodate the growing volume of requests that require reordering. This paper proposes FreeZone, an on-device writes reordering solution that extends the write buffer size by using the high-performance SLC flash region of storage. FreeZone allows the kernel to submit I/O requests freely, improving parallel write performance. Evaluation demonstrates that FreeZone achieves up to a 2.3× IOPS improvement compared with existing zoned storage architectures.

Retrieval-Augmented Generation (RAG) enhances Large Language Models (LLMs) by integrating information retrieval from knowledge databases, significantly improving the generated results' accuracy, relevance, and contextual richness. An in-depth analysis of RAG reveals that its diverse operations are primarily constrained by memory bottlenecks. The diversity and continual evolution of RAG algorithms further increase system design complexity. In this paper, we introduce RAGNMP, a general-purpose Near-Memory Processing (NMP) accelerator designed for RAG. Specifically, we first propose an enhanced and quantified elimination tree variant that simultaneously explores data placement, task parallelism, and pipelining to better support RAG workloads on NMP architectures. It also remains adaptable to algorithm changes in RAG. We further propose a general-purpose NMP architecture with a flexible processing unit that efficiently supports diverse memory-bound operations in RAG. Experimental results show that RAGNMP outperforms the state-of-the-art RAG system and accelerator.

As semiconductor technologies continue to scale toward advanced nodes, the sharp increase in transistor density has led to a substantial rise in on-chip power density, making thermal effects a first-order design concern. Traditional thermal mitigation techniques (e.g., thermal-aware coarse-grained floor-planning, thermal-aware (post-route) cell adjustment, and structural cooling enhancements) suffer from thermal prediction inaccuracy or incur high fabrication cost, limiting their practical applicability to modern SoC designs. To overcome the limitation, in this work, we present an ML-based early-stage thermal prediction and mitigation framework that enables proactive thermal management in the course of physical design process. Precisely, our approach (1) predicts first the power density map which is the underlying source of thermodynamic behavior during the global placement stage using machine learning models, and then (2) accurately estimates the steady-state thermal map through a physics-guided thermal interpolation. The predicted temperature is subsequently leveraged by (3) an ML-model based optimization engine that adjusts the placement solution to minimize thermal hotspots without timing degradation. Experimental results demonstrate that our proposed model achieves 49.0% and 34.9% accuracy improvement in power density and thermal prediction, respectively, compared to tool estimation. When applied to thermal-aware placement optimization, the framework successfully reduces the maximum chip temperature by 9.97◦C while maintaining equivalent timing and area. These results confirm the effectiveness of our proposed early-stage thermal modeling and optimization framework in improving thermal reliability for modern power-hungry SoCs.

Analog layout design remains heavily dependent on manual expertise, with placement being the most critical stage that requires significant development time and domain knowledge. Current automated placement techniques face challenges in capturing expert design practices and fall short of practical deployment. To address this limitation, we present AlphaPlacer, a novel MCTS-based analog placement framework that learns from historical layouts to provide expert-guided placement optimization. Our approach formulates analog placement as a hierarchical sequence pair search with a two level MCTS structure, embedding a pretrain learning framework that captures sequence pair distributions from expert layouts to guide the search toward high quality solutions. Experimental results demonstrate that our method significantly outperforms existing baselines across multiple key metrics including area, wirelength, and post-layout performance.

The prevalence of nonlinear systems in safety-critical domains calls for controllers with safety guarantees, while vision-based control relies on high-dimensional images complicates both decision-making and formal safety analysis under uncertainty. This paper proposes a provably safe controller synthesis method for vision-based neural network control systems. We first employ a conditional generative adversarial network (cGAN) to approximate the mapping from system states to visual observations and combine it with RL-based pretraining to build a verifiable closed-loop structure. A data-driven model quantifies uncertainties from environmental perturbations, while martingale theory guides the learning of a stochastic barrier certificate (SBC) to provide rigorous probabilistic safety bounds. Furthermore, counterexamples from verification are used to alternately refine both the controller and certificate networks, ultimately yielding a controller with formally provable probabilistic safety guarantees. Experimental results on widely studied benchmarks demonstrate the efficiency and effectiveness of our approach.

The Gottesman–Kitaev–Preskill (GKP) encoding is a promising approach for realizing fault-tolerant continuous-variable (CV) photonic quantum computers. Recent studies have investigated various GKP decoding algorithms, among which correlation-aware methods that exploit inter-qubit correlations achieve significantly improved error-correction performance. However, hardware implementation of GKP decoding remains largely unexplored. Error decoding in CV photonic quantum computers must operate within tens of nanoseconds to match the optical clock frequency. A straightforward hardware implementation of correlation-aware decoding introduces substantial computational latency due to its arithmetic complexity. To address this challenge, this paper proposes a high-accuracy and low-latency accelerator architecture optimized for correlation-aware GKP decoding. Logic synthesis using 7-nm FinFET technology demonstrates that our decoder can complete correlation-aware GKP decoding with in 12.96 ns. In addition, comprehensive design space exploration is conducted to evaluate tradeoffs among decoding accuracy, latency, and circuit area, leading to design guidelines for future correlation-aware GKP decoder implementations.

The growing demand for high-performance yet energy-efficient systems has elevated the need for coordinated power and signal routing in multilayer printed circuit boards (PCBs). While prior work optimizes either the power-delivery network (for DC IR-drop compliance) or signal routing (for routability), these separated flows often induce spatial contention and inefficient layer utilization. We propose the first unified rail-signal co-design framework for multilayer PCBs that jointly optimizes routing quality and power integrity. Our approach (1) generates routing guides to profile and allocate resources, (2) performs iterative rail-signal co-optimization that explicitly models crossing, overflow, and current density, and (3) conducts detailed routing via a guided, crossing-aware A* search that aligns with globally optimized guides. Experiments demonstrate that our proposed framework substantially improves routability while satisfying DC IR-drop constraints, delivering robust solutions with efficient resource usage.

Design of large-scale integrated circuits requires rigorous power integrity (PI) analysis to ensure reliable and robust operation. In particular, Direct Current (DC) PI analysis entails solving massive symmetric positive definite (SPD) systems derived from Kirchhoff's current law. Traditional PI evaluation methods are computationally expensive, making it difficult to satisfy the stringent turnaround-time requirements of modern design iterations. To address these challenges, we introduce PIANO, a physics-informed admittance neural operator for fast and high-fidelity DC PI analysis in 3D IC. PIANO first extracts an equivalent resistive network from the PDN layout and represents it as a graph. A graph neural network then learns the equivalent port admittance matrix between voltage-source ports and current sinks. The resulting reduced SPD system, formed from the predicted admittance matrix, is efficiently solved by a lightweight numerical solver to obtain port voltages. Experiments on industrial-scale PDNs show that PIANO achieves a 12.6x speedup over commercial simulators with only 1.95% voltage error, and a 17.2x acceleration when integrated into a PI-constrained design space exploration flow.

Mixture-of-Experts (MoE) models are attractive for large-scale inference, but sparse activation and skewed, time-varying expert popularity lead to cost-inefficiency. Serverless computing has become an attractive way due to its fine-grained resource elasticity and billing. Even so, achieving cost-efficient and SLO-compliant scaling for each expert with intra- and inter-layer dependencies under concurrent requests remains fraught with challenges. In this paper, we present sMoE, a topology-aware elastic auto-scaler for serverless MoE inference. Our insight is treating the deployment of a MoE inference pipeline as a DAG of experts and non-MoE segments. Building on this, sMoE is designed as a deep reinforcement learning-based solution. Specifically, it encodes expert- and layer-level runtime features with DAGNN by propagating cross-layer semantics. Coupled with a layer-wise pointer network, sMoE captures intra-layer semantics to jointly decide vertical resources, replica counts, and concurrency settings for each of all experts at runtime. Experimental results show that sMoE reduces serving cost by 21.4%–39.2% compared to state-of-the-art solutions, while meeting stringent end-to-end P95 latency SLOs.

Automatic transistor sizing remains a significant challenge in modern analog and mixed-signal circuit design. While recent AI-driven methods show promise, they remain sample-inefficient, largely because they struggle to effectively incorporate expert knowledge and generalize across different designs. We propose Stochastic Diffusion Prior (SDP), a framework that systematically bridges this gap. SDP elicits domain expertise through an intuitive interface based on the established gm/ID methodology, formally integrating this knowledge into the optimization. Critically, SDP is not a static prior; it enables dynamic adaptation through a novel mutual information-guided diffusion process, allowing the prior to be refined and corrected by new simulation data. SDP can be integrated with virtually any optimization method, enhancing its sample efficiency and exploration capabilities. Experimental validation on practical analog circuits demonstrates SDP's superiority over state-of-the-art approaches. When integrated with a simple Vanilla BO, SDP achieves up to 92.3× speedup (27.9× on average) while improving key performance metrics by up to 2.0× (1.5× on average). The approach maintains high effectiveness even with imperfect prior knowledge and successfully enables knowledge transfer between technology nodes, positioning it as a versatile and robust enhancement for circuit optimization.

Deploying Retrieval-Augmented Generation (RAG) on edge devices is in high demand, but is hindered by the latency of massive data movement and computation on traditional architectures. Compute-in-Memory (CiM) architectures address this bottleneck by performing vector search directly within their crossbar structure. However, CiM's adoption for RAG is limited by a fundamental ``representation gap,'' as high-precision, high-dimension embeddings are incompatible with CiM's low-precision, low-dimension array constraints. This gap is compounded by the diversity of CiM implementations (e.g., SRAM, ReRAM, FeFET), each with unique designs (e.g., 2-bit cells, 512x512 arrays). Consequently, RAG data must be naively reshaped to fit each target implementation. Current data shaping methods handle dimension and precision disjointly, which degrades data fidelity. This not only negates the advantages of CiM for RAG but also confuses hardware designers, making it unclear if a failure is due to the circuit design or the degraded input data. As a result, CiM adoption remains limited. In this paper, we introduce CQ-CiM, a unified, hardware-aware data shaping framework to jointly perform Compression and Quantization, flexibly shaping data to fit various CiM designs. To the best of our knowledge, this is the first work to shape data for comprehensive CiM usage on RAG.

This paper presents a new approach for minimising Boolean circuits subject to delay constraints. The proposed approach extends the efficient but purely area-based Boolean circuit minimiser eSLIM. The eSLIM minimiser reduces circuits by iteratively computing optimal replacements for small subcircuits on the fly. We extend the SAT encoding used, for synthesising these replacements, to take account for delay. While the additional constraints on delay restrict the set of possible candidates for the replacement, we can still harness the flexibility of making use of Boolean relations and multi-output circuits. We implemented the proposed method as part of the industrial-strength tool ABC. Surprisingly, in an experimental evaluation our implementation showed only a rather small deterioration in terms of area improvement, but substantial improvements in terms of delay compared to the purely area-based eSLIM approach on different benchmark sets.

DONNs leverage light propagation for efficient analog AI and signal processing. Advances in nanophotonic fabrication and metasurface-based wavefront engineering have opened new pathways to realize high-capacity DONNs across various spectral regimes. Training such DONN systems to determine the metasurface structures remains challenging. Heuristic methods are fast but oversimplify metasurfaces modulation, often resulting in physically unrealizable designs and significant performance degradation. Simulation-in-the-loop optimizes implementable metasurfaces via adjoint methods, but is computationally prohibitive and unscalable. To address these limitations, we propose SP2RINT, a spatially decoupled, progressive training framework that formulates DONN training as a PDE-constrained learning problem. Metasurface responses are first relaxed into freely trainable transfer matrices with a banded structure. We then progressively enforce physical constraints by alternating between transfer matrix training and adjoint-based inverse design, avoiding per-iteration PDE solves while ensuring final physical realizability. To further reduce runtime, we introduce a physics-inspired, spatially decoupled inverse design strategy based on the natural locality of field interactions. This approach partitions the metasurface into independently solvable patches, enabling scalable and parallel inverse design with system-level calibration. Evaluated across diverse DONN training tasks, SP2RINT achieves digital-comparable accuracy while being 1825 times faster than simulation-in-the-loop approaches. By bridging the gap between abstract DONN models and implementable photonic hardware, SP2RINT enables scalable, high-performance training of physically realizable meta-optical neural systems.

Analog placement with compact representations is traditionally solved using heuristic or simulated annealing methods that are difficult to integrate with a differentiable optimization engine. This paper introduces DiffSP, a differentiable sequence-pair-based analog placement method that bridges discrete combinatorial representation with continuous gradient optimization. We derive a smooth relaxation of the sequence pair constraint graph via Gumbel–Sinkhorn relaxation, which allows area, wirelength, and symmetry objectives to be jointly optimized via automatic gradient calculation. A MILP-based legalization stage then enforces exact geometric and symmetry constraints. Experiments on industrial-level OTA benchmarks show that DiffSP achieves better placement quality and post-layout performance metrics than state-of-the-art analog placers with significantly reduced runtime.

Although increasingly deployed for in-orbit earth observation (EO) imagery, existing neural image compression, following the design for natural images, struggles due to (1) a clear semantic structures gap and (2) computational inconsistencies between different in-orbit and ground hardware induce decoding errors. Observing EO imagery is dominated by large, semantically coherent regions (e.g., forest, urban), we propose SemCom, which uses a semantically partitioned codebook for efficient, region-aware bit allocation. SemCom introduces semantic-adaptive entropy coding with offline probability estimation, ensuring a fixed, platform-agnostic probability model for bit-exact decoding. Experiments on real-world satellite payloads show SemCom outperforms SOTA baselines with low in-orbit complexity.

RTL-3D enables early-stage cross-tier timing analysis and optimization in 3D ICs. The framework utilizes a Transformer-based pre-synthesis timing analysis model to directly steer its core partitioning method, which features differentiable register tier partitioning. This creates a tight feedback loop between timing prediction and physical implementation, closing the loop for co-optimization. The experimental evaluation demonstrates that RTL-3D achieves significant improvements in sign-off timing metrics by a 59.3% reduction in WNS and a 75.4% reduction in TNS compared to state-of-the-art methods.

Graph neural networks (GNNs) show strong promise for circuit analysis, but scaling to modern large-scale circuit graphs is limited by GPU memory and training cost, especially for deep models. We revisit deep GNNs for circuit graphs and show that, when trainable, they significantly outperform shallow architectures, motivating an efficient, domain-specific training framework. We propose Grouped-Sparse-Reversible GNN (GSR-GNN), which enables training GNNs with up to hundreds of layers while reducing both compute and memory overhead. GSR-GNN integrates reversible residual modules with a group-wise sparse nonlinear operator that compresses node embeddings without sacrificing task-relevant information, and employs an optimized execution pipeline to eliminate fragmented activation storage and reduce data movement. On sampled circuit graphs, GSR-GNN achieves up to 87.2\% peak memory reduction and over 30$\times$ training speedup with negligible degradation in correlation-based quality metrics, making deep GNNs practical for large-scale EDA workloads.

Approximate Nearest Neighbor Search (ANNS) at scale is constrained by the memory wall. By moving compute to memory, Processing-in-Memory (PIM) offers ample internal bandwidth but limited on-die compute, making arithmetic reduction crucial. We propose Prism, a PIM-based ANNS system co-optimizing vector pruning, distance evaluation, and host-PIM orchestration. It employs a proximity-aware vector pruner to leverage high intra-PIM bandwidth and dual-cluster affiliations to filter out distant vectors. Prism then performs sensitivity-ordered distance computation, prioritizing high-impact dimension segments and early terminating candidates once exclusion criteria are met. A stall-free host-PIM pipeline overlaps query preparation, PIM execution, and global ranking to sustain high throughput. Experiments show that Prism achieves 2.7-19.8x higher throughput over state-of-the-art systems.

Targeted bit-flip attacks (BFAs) exploit hardware faults to manipulate model parameters, posing a significant security threat. While prior work targets single-step inference models (e.g., image classifiers), LLM-based agents with multi-stage pipelines and external tools present new attack surfaces, which remain unexplored. This work introduces Flip-Agent, the first targeted BFA framework for LLM-based agents, manipulating both final outputs and tool invocations. Our experiments show that Flip-Agent significantly outperforms existing targeted BFAs on real-world agent tasks, revealing a critical vulnerability in LLM-based agent systems.

Glass interposers enable 5.5D chiplet stacking, offering an advance beyond silicon-based technology. However, routing in such dense, double-sided environments is challenging, and existing methods do not account for glass interposer design rules. To address this, we propose a 5.5D RDL routing algorithm. It begins by allocating routing resources, employs double-sided global routing for efficient guidance, and uses a novel pixel-based detailed routing to finalize results. Experiments show the proposed method achieves 100% routability and reduces wirelength by 37% compared to a 2.5D RDL router.

Neural networks are widely deployed at the edge to process high- dimensional sensor data, but they are susceptible to burst errors that can corrupt weights and degrade inference accuracy. Conventional error-correcting codes (ECC) mitigate errors but incur significant memory overhead. Recent ECC methods for neural networks over- write the least significant bits of the model weights with parity bits, providing zero-overhead resilience at the expense of slightly re- duced inference accuracy. In this paper, we propose a framework for Embedded and Efficient Error-Correcting Code for Error-Resilient Neural Networks called (E3-CODE). The proposed method embeds multi-bit parity within the entire weight representation, which is different from only modifying the LSBs of the weights. To mini- mize the negative impact from the parity embedded ECC, weight and parity assignments are jointly optimized via a mixed-integer linear programming (MILP) formulation. We also propose a hybrid ECC scheme that combines the embedded ECC with conventional ECC to trade-off minor memory overhead for significantly im- proved reliance. The experimental evaluation on the ImageNet and CIFAR-10 datasets using ResNet, MobileNetV2, and EfficientNet-B0 demonstrates that E3-CODE maintains software-level accuracy in the presence of burst errors. Compared with prior methods, the lifetime of the edge system is extended by 4.8𝑋 with no memory overhead and 10𝑋 with less than 2% memory overhead.

Diffusion model deployment has been suffering from high energy consumption and inference latency despite its superior performance in visual generation tasks. Dynamic voltage and frequency scaling (DVFS) offers a promising solution to exploit the potential of the underlying accelerators. However, existing approaches often lead to either limited efficiency gains or degraded output quality because they overlook the inherent fault tolerance of the diffusion model. Therefore, in this paper, we propose DRIFT, a novel algorithm-architecture co-optimization framework that harnesses the fault tolerance for efficient and reliable diffusion model inference. We first perform a comprehensive resilience analysis on representative diffusion models. Building on these observations, we introduce a fine-grained, resilience-aware DVFS strategy that selectively protects error-sensitive network blocks, and a rollback-ABFT mechanism that adaptively corrects only critical errors by reverting to previous timesteps. We further optimize offloading intervals and reorganize data layouts to reduce memory overhead. Experiments across diverse models and datasets show that DRIFT can achieve on average 36% energy savings through voltage underscaling or 1.7x speedup via overclocking while maintaining generation quality.

Fault injection attack (FIA) poses a severe threat to accelerators executing privacy-preserving homomorphic encryption (HE) neural networks. Defending against FIAs in the ciphertext domain is challenging due to opaque internal states and the difficulty of distinguishing inherent encryption noise from malicious perturbations. We propose Runtime-ADAR, a lightweight runtime framework enabling closed-loop detection and recovery fully within the ciphertext domain. By repurposing intrinsic HE noise as a high-fidelity diagnostic signal, Runtime-ADAR integrates a sparse-projection noise detector for statistical anomaly sensing and a gradient-field repair engine for in-situ weight compensation. This synergy transforms encryption noise from a vulnerability into a defensive asset. Evaluations on multiple encrypted models show that Runtime-ADAR mitigates over 90% of attack successes and restores up to 97% baseline accuracy with modest performance overhead on CNNs.

Optical proximity correction (OPC) is essential for mitigating lithographic distortions in semiconductor manufacturing. A standard OPC iteration involves the rasterization, lithography simulation, and correction of mask patterns. However, the non-differentiable nature of rasterization limits both optimization efficiency and flexibility. In this paper, we propose DR. OPC, a fully differentiable OPC pipeline enabled by differentiable rasterization. It natively supports advanced features like curvilinear patterns, multi-segment solving, process window improvement, and mask rule violation correction. Experiments demonstrate that DR. OPC achieves reductions of 52.1\%, 16.0\%, and 21.1\% in L2 error, PVB, and EPE, respectively.

With the scaling of switching chips, modular architectures are becoming mainstream. As a result, buffers become physically distributed across tiles, leading to poor utilization under imbalanced traffic. To address this, we propose CrediX, a lightweight dynamic buffer management mechanism that aggregates distributed buffers into region-based shared pools and allocates usage on demand through a Regional Credit Allocator (RCA). The design leverages existing credit-based flow control and preserves packet ordering via a simple VC-to-path mapping. Evaluations show that CrediX reduces backpressure by 65.6% under synthetic Hotspot traffic and mitigates severe hotspot occupancy in a realistic workload.

In semiconductor manufacturing, defect analysis is essential, but manual inspection cannot scale. However, existing automated inspection methods remain insufficient for root-cause analysis and process optimization. To this end, we present SePArate, a weakly supervised wafer defect segmentation method. SePArate enables pixel-level separation of patterns by leveraging only image-level annotations. It consists of a three-phase training: encoder pretraining, knowledge transfer to learn spatial cues, and training on synthetic mixed-defect data for accurate segmentation. Experiments demonstrate that SePArate significantly outperforms the baselines.

Co-optimizing timing and power in modern VLSI designs remains challenging under realistic static timing analysis and standard-cell libraries. Classical gate sizing often scales poorly, while learning-based sizers behave as expensive black boxes with limited generality. Recent differentiable physical optimization enables gradient-based design flows, but existing approaches still struggle to stay aligned with library-based implementations and to provide controlled timing–power trade-offs. We propose a library-native quad-gradient gate sizing framework that leverages differentiable timing to derive structured guidance for timing and power, enabling more systematic and interpretable co-optimization in the standard-cell sizing space. On the ICCAD 2025 contest benchmarks, our framework achieves, on average, 40.4 percent points (%pt) larger reduction in TNS and 16.2 %pt better total power change than the 1st-place contest flow.

Cloud–edge AI deployments must balance compression and security on resource-limited devices. While Tensor-Train Decomposition (TTD) is widely used to compact models, encryption research targets dense networks, leaving the practicality of selective encryption under compression unclear. We introduce TT-SEAL, the first selective encryption scheme tailored to TT-decomposed networks. TT-SEAL ranks TT cores using a core-wise importance criterion and encrypts a minimal set of critical cores with AES, cutting decryption cost while retaining robustness to adversarial transfer comparable to full encryption. FPGA-based experiments show encrypting as little as 4.89% of parameters preserves robustness while reducing the share of AES decryption overhead in end-to-end inference to low single digits, enabling secure, low-latency inference.

High-Level Synthesis (HLS) is a pivotal electronic design automation (EDA) technology that enables the generation of hardware circuits from high-level language descriptions. A critical step in HLS is Design Space Exploration (DSE), which seeks to identify high-quality hardware architectures under given constraints. However, the enormous size of the design space makes DSE computationally prohibitive. Although numerous algorithms have been proposed to accelerate DSE, our extensive experimental studies reveal that no single algorithm consistently achieves Pareto dominance across all problem instances. Consequently, the inability of any single algorithm to dominate all benchmarks necessitates an automated selection mechanism to identify the best-performing DSE algorithm for each specific case. To address this challenge, we propose the SoberDSE framework, which recommends suitable algorithm based on benchmark characteristics. Experimental results demonstrate that our SoberDSE framework significantly outperforms state-of-the-art heuristic-based DSE algorithms by up to 5.7 \times and state-of-the-art learning-based DSE methods by up to 4.2 \times. Furthermore, compared to conventional classification models, SoberDSE delivers superior accuracy in small-sample learning scenarios, with an average enhancement of 35.57\%. Code and models are available at \url{https://anonymous.4open.science/r/Sober-4377}.

Computation graphs are fundamental for GPUs to efficiently deploy workloads. They also bring a challenge of growing memory demands. Operator recomputation and operator fission are promising directions to mitigate peak memory usage. However, existing work relies on offline decisions in recomputation and fission, leading to a increase in computation latency for only a marginal reduction in memory usage. In this paper, we propose PRICE, which is a novel operator recomputation and fission framework for computation graphs. Central to this framework is the attainable arithmetic intensity that can effectively trade off between memory usage and computation latency. We design a compile-time modeling approach to parameterize arithmetic intensity with GPU workload characteristics. Then we develop a runtime instantiation approach to attain the arithmetic intensity for online decision-making. Experiments on NVIDIA RTX 4090 and A100 demonstrate that PRICE achieves 1.08× to 1.31× speedup while delivering a comparable reduction in peak memory usage, compared to the state-of-the-art work.

The combinatorial explosion of directives in high-level synthesis (HLS) creates an expansive design space. Previous efforts to construct design space exploration (DSE) methods with heuristics struggle to identify Pareto-optimal designs under tight search budgets. Therefore, we introduce ParetoPilot, an automated DSE framework, which leverages a dedicated LLM to adopt global optimization reasoning to navigate exploration. Guided by optimization strategies, ParetoPilot integrates directive scheduling and quality awareness to rapidly shape broad and concave Pareto fronts. Compared to a SOTA heuristic-based DSE method, ParetoPilot improves DSE performance by 49.5% and achieves 1.8× efficiency gain, outperforming the auxiliary LLM DeepSeek-R1 by 81.4%.

To perform design space exploration (DSE) of spatial architectures for LLM workloads, we propose FSGen, an agile generator and estimation framework. FSGen targets the key optimization spaces of fused-operator dataflows and multi-level sparsity. Fused operator boosts performance by more than 10x with minimal effect on other PPA metrics, and power is improved by 1.4x with similar performance. We propose early-stage models with less than 12.8% error, which drastically reduce DSE runtime. We identify optimal designs and compare their optimized performance against several hardware generators, achieving 58x better efficiency. The source code of FSGen is available online.

This paper introduces RTL-BenchMT, an agentic framework for dynamic maintenance of RTL generation benchmarks. Large Language Models (LLMs) for automated RTL generation are one of the most important directions in EDA research, yet current RTL benchmarks face two critical challenges: (1) flawed cases in the benchmarks and (2) overfitting to the benchmarks. Both challenges are difficult to resolve purely by manual engineering effort. To address these issues and systematically reduce human maintenance cost, we propose an automated agentic framework, RTL-BenchMT. RTL-BenchMT focuses on two key applications: (1) automatically identifying and revising flawed benchmark cases and (2) automatically detecting and updating overfitting cases. With the assistance of RTL-BenchMT, we conduct a thorough, in-depth analysis of flawed and overfitting cases and produce a refined benchmark suite that will be open-sourced to the community.

Superconducting Rapid Single Flux Quantum (RSFQ) logic is a promising candidate for high-performance computing due to its ultra-high speed and ultra-low power. Since most RSFQ logic gates require synchronization with a single clock pulse, RSFQ circuits have a clock-driven gate-level pipelined architecture in nature. However, the gate-level pipelined architecture leads to layouts with a high width-to-height ratio, especially in large circuits, because the layout width increases with the number of logic stages while the height is determined by the tallest column. To address this, we propose JSPlace, a shape-controllable and length-matching placement algorithm for RSFQ circuits. Our algorithm folds the multi-stage pipelined placement into three segments and merges columns via mixed-integer linear programming (MILP) to achieve the target width-to-height ratio. Subsequently, dynamic programming determines the vertical positions of nodes within each column, followed by connectivity-driven repositioning to minimize total vertical wirelength. Experimental results on ISCAS85 and EPFL benchmarks demonstrate that JSPlace achieves effective control of layout width-to-height ratio while significantly outperforming the state-of-the-art in layout area and wirelength.

Function-as-a-Service (FaaS) has become a de-facto paradigm for deploying cloud applications, yet it exposes sensitive data to untrusted infrastructures. Running functions on confidential virtual machines (CVMs) such as Intel TDX provides strong isolation for data but significantly increases cold-start latency due to CVM initialization. This paper presents TDSnap, the first TDX-aware function snapshot system that records a verified function state with its TD and restores it on demand. Using snapshot-bounded attestation and TD-aware working-set identification, TDSnap preserves TDX isolation while reducing cold-start latency. Evaluation shows that TDSnap reduces cold-start latency by up to 40x and matches non-TDX snapshot systems.

Accurate timing prediction at the register-transfer level (RTL) is a longstanding challenge in design automation. Existing graph-based methods struggle with limited receptive fields, high complexity, and a lack of signal directionality. We present RTL-Sequencer, a novel sequence-based paradigm that enables scalable RTL timing prediction via linearizing logic cones by breadth-first traversal and applying modern linear sequence models. Furthermore, sequence models are customized by four synergistic techniques, including sequence shuffling, bidirectional modeling, differentiable modeling, and a hybrid graph-sequence architecture. Extensive experiments demonstrate significant improvements of RTL-Sequencer over state-of-the-art baselines, advancing early-stage timing optimization.

Fully homomorphic encryption (FHE) allows direct computation on encrypted data and thus enables privacy-preserving computation in the cloud. Among FHE schemes, CKKS efficiently supports arithmetic computation, while TFHE excels in logic operations. Recent studies have attempted to develop unified FHE accelerators that support diverse computational tasks and leverage the complementary strengths of the two schemes. However, existing unified FHE accelerators are predominantly CKKS-centric. At the operator layer, TFHE is mapped onto CKKS-oriented operators, causing significant performance degradation. Furthermore, the invocation to functional units and memory is entirely dominated by CKKS, resulting in hardware underutilization for TFHE. In this paper, we propose three coordinated co-optimizations to address these challenges. First, we unify the computation of Fast Fourier Transform (TFHE core operation) and Number Theoretic Transform (CKKS core operation), and design a dual-mode computational flow to efficiently support both computations. Second, we propose an aggressive strategy of bootstrapping key unrolling to maximize TFHE hardware utilization. Third, we design a hardware-oriented support for FFT Shrinking KeySwitch to mitigate the performance bottleneck of TFHE KeySwitch. Accordingly, we present Chimera, a unified accelerator that redesigns the functional units and memory organization for TFHE to efficiently support these optimizations. Lastly, we develop an error, memory, and bandwidth-constrained auto-tuning framework that derives optimal TFHE configurations to maximize TFHE hardware utilization. Compared with the state-of-the-art unified FHE designs, Chimera achieves an average performance improvement by 14.84x across TFHE workloads, while maintaining comparable performance on CKKS workloads, with only a 9.6% area increase.

Model checking, especially symbolic algorithms such as IC3/PDR, is a powerful verification technique but is increasingly constrained by single-threaded performance. Existing parallel model checking approaches either rely on redundant portfolio executions or suffer from scalability bottlenecks caused by centralized scheduling. We propose a new parallel paradigm for model checking based on fine-grained task decomposition and a decentralized Work-pulling architecture. A distributed concurrent task repository replaces the central coordinator, enabling worker threads to autonomously acquire tasks and naturally achieve dynamic load balancing. We present the framework design, analyze its parallel mechanisms, and evaluate its performance on representative benchmarks. Our approach achieves notable speedup and demonstrates solid scalability over serial execution.

Fully homomorphic encryption (FHE) enables direct computation on encrypted data that ensures robust privacy protection for machine learning systems. However, the substantial computational overhead of FHE necessitates efficient acceleration techniques for practical deployments. In GPU-accelerated homomorphically encrypted neural network (HENN) inference, we observe that the primary performance bottleneck shifts from computation to memory transfer due to huge memory footprints w.r.t. the limited device memory. To address this, we propose a memory-aware design framework to fully utilize GPU memory by adaptively trading computation for reduced memory footprint. Our framework introduces a static model to estimate memory footprint and latency for HENN inference. We propose an automatic design space exploration framework to generate optimal cryptographic, bootstrapping, and encoding configurations, thereby effectively minimizing execution latency with the given GPU memory capacity. Experiments with homomorphically encrypted ResNet-20 and ResNet-18 across various GPU devices show up to 4.97$\times$ speedup with a 91.88\% reduction in memory footprint. It also demonstrates the first deployment of full-fledged homomorphically encrypted ResNet-20/18 at 128-bit security level on an RTX~4060~Ti GPU with 16 GB of device memory.

With the deceleration of Moore's Law, three-dimensional (3D) integration via hybrid bonding enables higher performance.However, existing 3D placers exhibit limitations: pseudo-3D placers suffer from modeling inaccuracies, while true-3D placers neglect timing closure.Prior 3D static timing analysis (STA) lacks accurate parasitic modeling, impeding timing optimization.This paper presents the first timing-driven true-3D placement framework for hybrid-bonding-based integrated circuits.We develop a 3D STA engine with accurate parasitic modeling and integrate a sample-based 3D wirelength model with hybrid weighting for global placement, followed by Lagrangian-based detailed placement.Results demonstrate 30-1002x reduction in TNS and 3-14x reduction in WNS over state-of-the-art placers.

Accurate power analysis is critical in VLSI design, as it directly impacts power optimization strategies. However, traditional approaches are often hindered by the substantial runtime required for per-cycle toggle propagation in the netlist, which propagates register toggle information through combinational logic. To address this, we propose LEAP, the first work to enable per-cycle toggle propagation prediction with both high accuracy and efficiency. This is achieved through a novel, linear-complexity graph transformer capable of simulating toggle propagation, along with specially designed self-supervised pre-training tasks that enable the model to capture circuit structure and functionality. LEAP achieves a 7.6x speedup over the EDA tool in toggle propagation, and attains a near-perfect area under the Precision-Recall curve (PR-AUC) of 0.99 for prediction results. Moreover, LEAP can be seamlessly integrated with other machine learning based power models into LEAP‑Power. This integration enables precise per‑cycle layout power prediction directly from post‑synthesis netlists, achieving a mean absolute percentage error (MAPE) of only 4.55%. By bypassing toggle propagation in the netlist, LEAP‑Power delivers substantial runtime gains, running 5.3x faster than the model without LEAP.

VLSI layout pattern generation plays a crucial role in design for manufacturability (DFM). Patterns that incorporate specific design rule checking (DRC) violations are valuable for applications such as foundry design-rule deck development, EDA tool validation, and generating training data for AI-based DRC research. However, existing research primarily focuses on producing DRC-clean layouts by enforcing rule compliance through constraints or filtering, while ignoring the generation of controllable violations. To address this gap, we propose DRCGen, a controllable framework for generating DRC violation patterns with cross-PDK transferability. DRCGen is based on a diffusion model with conditional control, generating structured control hints to encode spatial and semantic violation information for fine-tuning the model. The model can generate violation patterns of user-specified types within a target region based on a natural-language prompt, while maintaining DRC-compliance outside the region. Additionally, we incorporate few-shot learning to facilitate rapid transfer across different PDKs. Experimental results show that, compared to state-of-the-art methods, our approach achieves a 2.27× increase in topological diversity and a 1.02× increase in geometric diversity. Compared to Calibre LSG, we achieve 3.31× and 1.15× improvements in topological and geometric diversity, respectively.

Abstract—With the advancement of fully homomorphic encryption (FHE), encrypted applications exhibit diverse encryption parameters and computational characteristics. However, existing FHE accelerator architectures are typically fixed and lack the flexibility to efficiently support this diversity. The diversity among FHE applications imposes urgent demands on the flexibility and efficiency of accelerator design. To address this challenge, we propose Hades, an automated framework for FHE accelerator generation. Hades analyzes the dataflow graph and encryption parameters of a given FHE application, establishes a mapping from the application to hardware architecture, and automatically searches for accelerator configurations optimized for the target workload. The automation capability of Hades allows for flexible hardware realization on FPGAs and also provides design guidance for ASIC-based accelerators. We evaluate Hades on a range of FHE applications with diverse characteristics. Experimental results demonstrate that Hades can effectively exploit application-specific features to automatically generate efficient hardware architectures. We highlight the following results: (1) compared with state-of-the-art FPGA accelerators, Poseidon and FAB, speedup achieves 1.99× to 6.58× while reducing 50% resource consumption; (2) compared with state-of-the-art ASIC accelerators, SHARP and CraterLake, speedup achieves more than 3×; (3) achieves 65%-94% hardware utilization on multiple FHE applications, more than a 2× improvement over manual accelerators.

Providing deterministic timing guarantees, beyond merely optimizing the accuracy-latency trade-off, is a mandatory yet unaddressed challenge for ultra-low-power spiking neural networks (SNNs) in resource-limited, safety-critical systems. In this paper, we propose RT-SNN, a novel adaptive SNN methods that integrates a system-level scheduling framework for SNN-based multi-object detection that, for the first time, co-optimizes inference accuracy while providing these strict timing guarantees. RT-SNN orchestrates SNN inference at both frame and timestep levels, introducing flexible timestep control and a novel membrane potential reuse mechanism to enhance accuracy without increasing latency. Evaluations on the KITTI dataset show that RT-SNN significantly improves the accuracy and energy efficiency compared to both state-of-the-art SNNs and traditional ANNs. Furthermore, a case study on a ROS-based F1/10 autonomous vehicle testbed demonstrates its real-time efficacy, validating its practical deployment in safety-critical systems.

3D QLC NAND flash suffers from a slow two-step programming process. The problem is exacerbated by write invalidation on wordlines, which occurs when pages are updated between the two steps, wasting programming effort and degrading performance. While prior work offers partial mitigation, it fails to fundamentally address the root cause: the misalignment of page invalidation time within a wordline. In this paper, we propose WILL, a proactive page mapping scheme that enables write invalidation skipping for QLC NAND flash. The basic idea is to group pages with similar invalidation time into the same wordline and turn partially-invalid wordlines into fully-valid or fully invalid ones, thereby skipping the programming on fully-invalid wordlines. To achieve this, WILL first predicts page invalidation time, then organizes pages accordingly to maximize the opportunities of write invalidation skipping. Finally, WILL schedules short-lifespan data to wordlines requiring high-latency fine-step programming to increase the probability of skipping high programming latencies for further programming performance enhancement. In addition, read parallelism is maintained by identifying and excluding read-hot data from this mapping. Experimental results show that WILL reduces programming execution time by 10.0% compared with the state-of-the-art, along with skipping an additional 5.03% of fully-invalid wordlines and lowering the partially-invalid ratio by 15.9% on average, at a minimal read performance cost of 2.59%.

In this paper, we propose an analytical method for 3D mixed-size placement that incorporates macro-orientation awareness in face-to-face (F2F) terminal-bonded heterogeneous 3D ICs. This work introduces a novel one-pass placement framework that bypasses the conventional 2.5D co-optimization, effectively narrowing the gap between partitioning and placement and achieving significant time savings. Our method constructs a differentiable distributed macro-rotation system that unifies partitioning, placement, and macro-orientation within 3D global placement. To compensate for deviations arising from wirelength estimation in 3D placement, we further apply an FM-based post-partitioner. Experimental results on the ICCAD 2023 contest benchmark show that our approach achieves an 8% higher quality than the first-place contest entry and a 2% improvement against the best published method with 1.6× runtime speedup.

Sparse LU factorization is a critical kernel in scientific computing. Given its irregular data dependencies and complex computation patterns arising from inherent high sparsity, its acceleration remains largely unexplored on FPGAs. The high concurrency capability offered by High Bandwidth Memory (HBM) has recently presented new opportunities. Nevertheless, accelerating sparse LU factorization on HBM-equipped FPGAs remains non-trivial due to rigid dependency synchronization and imbalanced load. In this paper, we propose SALUT, a high-performance sparse LU factorization accelerator on HBM FPGAs. An asynchronous task activation mechanism is developed to pre-compile complex runtime data dependency resolution into fine-grained dependency management, reducing synchronization overhead and maximizing computation parallelism. Additionally, we design a hardware architecture facilitating stream-aware parallel scheduling by decoupling burdensome dependency resolution from task activation, eliminating serial bottleneck of a centralized scheduler. Finally, a locality-aware dual-queue load balancing strategy ensures data locality and high hardware utilization. Evaluations on 15 sparse matrices show that SALUT's geometric mean throughput and energy efficiency surpass the NVIDIA cuDSS solver by 4.0x and 6.5x on RTX A6000 GPU, and 3.7x and 4.7x on Tesla V100 GPU, respectively.

Nonlinear activation functions (NAFs) are critical to deep neural networks (DNNs), yet their diverse and complex computational forms are inherently hardware-unfriendly, incurring substantial latency, area, and energy overheads. This work presents UNICON, a unified reconfigurable hardware architecture that efficiently supports diverse NAFs through a logarithmic-domain computing paradigm. UNICON uncovers the intrinsic correlations among NAFs and decomposes complex nonlinear operations into lightweight shift–add operations. With modular design and dynamic reconfigurable dataflows, UNICON achieves high functional flexibility and resource efficiency without hardware duplication. As the first algorithm–architecture co-designed solution that unifies diverse NAFs within a logarithmic-domain framework, UNICON gains an average 1.55x speedup, 2.56x energy efficiency, and 2.74x area efficiency over state-of-the-art NAF architecture.

Analog circuit optimization is typically framed as black-box search over arbitrary smooth functions, yet device physics constrains performance mappings to structured families: exponential device laws, rational transfer functions, and regime-dependent dynamics. Offthe-shelf Gaussian-process surrogates impose globally smooth, stationary priors that are misaligned with these regime-switching primitives and can severely misfit highly nonlinear circuits at realistic sample sizes (50–100 evaluations). We demonstrate that pretrained tabular models encoding these primitives enable reliable optimization without per-circuit engineering. Circuit Prior Network (CPN) combines a tabular foundation model (TabPFN v2) with Direct Expected Improvement (DEI), computing expected improvement exactly under discrete posteriors rather than Gaussian approximations. Across 6 circuits and 25 baselines, structure-matched priors achieve R2 ≈ 0.99 in small-sample regimes where GP-Matérn attains only R2 = 0.16 on Bandgap, deliver 1.05–3.81× higher FoM with 3.34–11.89× fewer iterations, and suggest a shift from handcrafting models as priors toward systematic physics-informed structure identification. Our code will be made publicly available upon paper acceptance.

The high energy cost of video AIoT systems stems from redundant operations across sensing, transmission, and computation. While prior work optimizes individual stages, the lack of cross-stage coordination forces each stage to re-detect redundancy, limiting overall efficiency. We present DeltaSight, an algorithm–hardware co-design architecture that establishes a sensor-side unified redundancy criterion serving as the common basis for redundancy elimination throughout the pipeline. Algorithmically, we generate this criterion via sensor-side block-level redundancy detection whose output matches the granularity of downstream computation, complemented by a semantic-aware sampling strategy that adapts precision to task relevance. An architecture is designed to support this algorithm with minimal hardware additions. DeltaSight gains 2.4x sensor-side and 1.7x end-to-end energy efficiency, with slight accuracy improvements.

In modern very large-scale design, cell-level placement is prohibitively slow and memory-intensive, hindering rapid design-space exploration for integrated circuits. Cell-level placement consistently shows that cells within the same functional module tend to group together, making module-level placement a practical abstraction for fast yet accurate design estimation. To this end, we introduce a module-level placement framework with a force-directed soft-module deformation scheme, where functional modules are modeled as deformable entities that adapt aspect ratios under area preservation. This reduces the size of the problem by several orders of magnitude, while retaining high fidelity to cell-level placement. On industrial-scale benchmarks, our approach achieves a 56x average speedup over conventional placers, incurs only about 3% inter-module HPWL error, and recovers 93% of the top-10% longest nets. These results establish a practical and scalable solution for early-stage placement estimation.

Fully Programmable Valve Array (FPVA) biochips offer high flexibility and reusability for executing complex biochemical assays. However, their reliability and performance are constrained by the time-sensitive nature of bioassays and the inherent complexity of pressure-driven fluid routing. Existing methods often overlook timing constraints and the effects of pressure paths during early design stages, leading to suboptimal scheduling and placement. To address these limitations, we propose a timing-driven scheduling and placement framework that explicitly incorporates pressure-path interference to optimize fluidic operations, thereby reducing delays and resource overhead. Experimental results demonstrate that the framework significantly decreases bioassay completion time, fluid path length, and delays, enhancing both operational efficiency and system robustness.

Ambient energy harvesting technologies offer the promise of perpetual operation for batteryless Internet of Things (IoT) devices; however, their execution is frequently halted by unpredictable power failures. Traditional methods to ensure correctness, such as software checkpointing (e.g., Mementos) and newer systems for deep neural networks (e.g., DynBal), are burdened by substantial energy and latency overheads for progress preservation, limiting their use on ultra-low-power platforms. This paper introduces EnergyHDC, an energy-aware inference system designed for intermittent operation by integrating Hyperdimensional Computing (HDC). The system pairs HDC's algorithmic robustness with fine-grained energy adaptation using three key contributions: (1) an energy-proportional checkpointing that optimizes preservation granularity against available energy; (2) a dimension-first reordering that slashes per-checkpoint storage; and (3) a priority-based pruning that allows for compile-time energy-accuracy trade-offs. Evaluated on an MSP432P401R microcontroller platform under intermittent power, EnergyHDC demonstrates up to 214x speedup compared to Mementos. It also achieves 19.6x faster inference than DynBal under similar accuracy and realistic energy-harvesting conditions. These results validate that a co-design approach, coupling energy-aware execution with HDC's intrinsic robustness, can reframe intermittence from a system constraint into an opportunity for efficient edge intelligence.

Large Language Models (LLMs) are rapidly becoming the backbone of modern cloud services, yet their inference costs are dominated by energy consumption on GPUs. Unlike traditional GPU workloads, LLM inference consists of two distinct stages with different characteristics: the prefill phase, which is latency-sensitive and scales quadratically with prompt length, and the decode phase, which progresses token by token with undetermined length. Current GPU power governors (for example, NVIDIA default) overlook this asymmetry, treating both phases uniformly. The result is mismatched voltage/frequency settings, leading to suboptimal voltage/frequency configurations, head-of-line blocking, and excessive energy consumption. We introduceGreenLLM, a Service-Level Objectives (SLO) aware serving framework that minimizes GPU energy by explicitly separating prefill and decode control. At ingress, requests are routed into length‑based queues so short prompts avoid head‑of‑line blocking, tightening TTFT. For prefill, GreenLLM collects short traces on a GPU node, fits compact latency–power models over SM frequency, and solves a queueing‑aware optimization to pick energy‑minimal clocks per class. During decode, a lightweight dual‑loop controller tracks throughput (tokens-per-second) and adjusts frequency with hysteretic, fine‑grained steps to hold tail TBT within target bounds. Across Alibaba and Azure trace replays, GreenLLM achieves up to 34% reduction in total energy consumption compared to the default DVFS baseline in Alibaba/Azure trace replays, with no loss of throughput and only less than 3.5% SLO violations increase, demonstrating its effectiveness in the efficient LLM service.

Modern zero-knowledge proof (ZKP) schemes are moving from costly elliptic curve-based systems towards algebraic proof systems. This transition is ushering in a new era of broad adoption of hardware-friendly ZKPs, implementable even on resource-constrained edge devices. Algebraic structures, such as towers of binary fields, are core components of such schemes, and they require hardware and algorithmic innovation to realize advanced ZKPs, such as Binius and Binius-FRI, efficiently. Hence, this paper introduces the ATTINA framework, a high-throughput additive number theoretic transform (ANTT) accelerator operating over extended binary fields. ANTT is the most computationally intensive task for realizing Binius. ATTINA partitions ANTT tasks into multiple subtasks and strategically allocates them to processing elements (PEs) and hardware programmable logic (PL) kernels in an interleaved computing pattern. ATTINA features a scalable architecture that enables dynamic parameter changes for different cryptographic applications. To understand its applicability, this paper implements ATTINA on an edge-deployable heterogeneous Versal adaptive system-on-chip (ASoC) platform. ATTINA on Versal ASoC maintains a throughput of 10 Gb/s. ATTINA outperforms a benchmark CPU implementation of ANTT on a high-end processor (i9-14900K) by \textbf{139$\times$} and a PE-only implementation by \textbf{38$\times$} in terms of latency while operating at $\ leq$5W for a 4096-point ANTT. ATTINA's code is published at \url{https://anonymous.4open.science/r/ATTINA} for evaluation and reproducible research.

Sparsity has become a defining characteristic of modern workloads, motivating the development of specialized accelerators to mitigate the challenges inherent to sparsity. Sparse streaming accelerators have proved to be an effective solution, yet current designs are restricted to single-workload execution. Additionally, they exhibit significant underutilization in processing elements (PEs) due to their underlying non-zero scheduling strategies. To address these limitations, we propose Procyon, a fine-grain multi-tenancy framework that fuses the PE instruction streams of multiple workloads into a unified execution schedule. This allows instructions from different workloads to execute on the same PE, thereby, improving its utilization and enabling concurrent execution of multiple workloads on a single accelerator instance. We evaluate Procyon on AMD Alveo U55C FPGA using workloads from the SuiteSparse dataset and show that it substantially reduces PE underutilization that results in 3x speedup over state-of-the-art sparse streaming accelerators (Serpens and Chason), and reaches a peak throughput of 61.2 GFLOP/s.

Secure multi-party computation (MPC) offers a practical foundation for privacy-preserving machine learning at the edge. However, current MPC systems rely heavily on communication and computation-intensive primitives-such as secure comparison-for nonlinear operations, which are often impractical on resource-constrained platforms. To enable real-time secure inference, we introduce a highly efficient, TEE-accelerated framework for secure comparison. Specifically, we reduce communication cost by redesigning the core primitives-leaf comparison and merge-so that each completes in a single round of interaction, reducing the round complexity from log(n) to just 1 per operation. Furthermore, unlike prior work that heavily relies on Oblivious Transfer (OT), a well-known computational bottleneck, we leverage synchronized seeds inside the TEE to eliminate OT for the vast majority of our designs, along with a correlated-randomness reuse technique that keeps new designs computationally lightweight. To fully realize the potential, we design a specialized accelerator that restructures the dataflow across stages to enable continuous, fine-grained streaming and high parallelism, reducing memory overhead. Our design achieves up to 4.86x speedup on ResNet-50 inference, compared with state-of-the-art CNN frameworks, and achieves up to 7.44x speedup on bert-base inference, compared with state-of-the-art LLM frameworks.

Diffusion models have revolutionized video generation, becoming essential tools in creative content generation and physical simulation. Transformer-based architectures (DiTs) and classifier-free guidance (CFG) are two cornerstones of this success, enabling strong prompt adherence and realistic video quality. Despite their versatility and superior performance, these models require intensive computation. Each video generation requires dozens of iterative steps, and CFG doubles the required compute. This inefficiency hinders broader adoption in downstream applications. We introduce GalaxyDiT, a training-free method to accelerate video generation with guidance alignment and systematic proxy selection for reuse metrics. Through rank-order correlation analysis, our technique identifies the optimal proxy for each video model, across model families and parameter scales, thereby ensuring optimal computational reuse. We achieve 1.87× and 2.37× speedup on Wan2.1-1.3B and Wan2.1-14B with only 0.97% and 0.72% drops on the VBench-2.0 benchmark. At high speedup rates, our approach maintains superior fidelity to the base model, exceeding prior state-of-the-art approaches by 5 to 10 dB in peak signal-to-noise ratio (PSNR).

General matrix multiplication (GEMM) is the computational back- bone of modern AI workloads, and its efficiency is critically depen- dent on effective tiling strategies. Conventional approaches employ symmetric tile buffering, where the buffered tile size of the input 𝐴 along the dimension 𝑀 matches the output tile size of 𝐶. In this paper, we introduce asymmetric tile buffering (ATB), a simple but powerful technique that decouples the buffered tile dimensions of the input and output operands. We show, for the first time, that ATB is both practical and highly beneficial. To explain this effect, we develop a performance model that incorporates both the benefits of ATB (higher arithmetic intensity) and its overheads (higher kernel switching costs), providing insight into how to select effective ATB tiling factors. As a case study, we apply ATB to AMD's latest XDNA2™ AI Engine (AIE), achieving up to a 4.54× speedup, from 4.8 to 24.6 TFLOPS on mixed-precision BFP16–BF16 GEMM, establishing a new performance record for XDNA2™ AIE.

Training satellite-edge deep learning models remains constrained by limited onboard resources and high data download latency. Although split federated learning (SFL) offers a potential solution through model partitioning, its convergence and robustness are fundamentally compromised by the intermittent and asymmetric satellite–ground links. To address these issues, we introduce SatSFL as a novel SFL system for satellite-based computing networks. SatSFL employs an interpolated gradient approximation to emulate ground feedback during disconnections, markedly accelerating convergence while maintaining robustness under heterogeneous data. In addition, we design adaptive uplink compression under asymmetric bandwidth to ensure that balanced and critical gradients are reliably transmitted back to satellites. We implement and evaluate SatSFL on real-world LEO satellite systems and datasets, demonstrating superior accuracy and convergence speed compared to state-of-the-art methods.

The generation of fluid-dynamics fields is essential for understanding complex nonlinear systems and enabling real-time scientific computing. Conventional computational fluid dynamics pipelines rely on finite-element or finite-volume solvers on von Neumann architectures, which discretize continuous physical evolution into many iterative updates, leading to prohibitive latency and energy consumption. Inspired by neural dynamical systems in the brain, we propose a biologically inspired continuous-time hardware–software co-design framework for flow-matching–based turbulent-flow generation. (1) The flow-matching model adopts an MLP-Mixer architecture that emulates cortical-style information integration and hierarchical signal mixing, providing a compact backbone that naturally aligns with closed-loop analog computation. (2) A fully analog continuous-time RRAM CIM neural ordinary differential equation (ODE) solver is developed to physically realize neural-like continuous-time latent dynamics, enabling high-speed and low-power flow generation. (3) Noise-aware training and decoder retraining are jointly introduced to ensure robust generation quality in the presence of RRAM read/write noise. Experiments on three turbulent-flow datasets show that the MLP-Mixer backbone matches convolutional and attention-based flow-matching models in velocity-field accuracy while mapping efficiently to CIM hardware, and that the proposed analog ODE solver reduces energy consumption by 98.24% and latency by 99.99% compared with an NVIDIA A100 GPU, while maintaining stable generation fidelity under realistic RRAM read/write noise. This work establishes a new paradigm for high-speed, energy-efficient physical process generation and scientific AI acceleration using neuromorphic continuous-time CIM computing.

The "memory wall'" problem continues to constrain modern applications, making scalable memory expansion via Compute Express Link (CXL) increasingly critical. While DRAM-Flash hybrid CXL systems offer a capacity solution, their performance remains hampered by inefficient access models. This paper presents CtxMem, an OS-hardware co-designed memory expansion system built on byte-addressable CXL interconnect and inexpensive flash storage. Unlike existing approaches, CtxMem introduces an asynchronous page fault-based mechanism that offloads the entire data plane of page fault handling to the CXL device. This is achieved through three key innovations: a dynamic direct-mapped cache that maximizes DRAM utilization, a lightweight hardware profiling unit enabling accurate and rapid hot/cold page identification with minimal overhead, and a OS-hardware co-designed page fault handling procedure that efficiently offloads data migration. Our GEM5-based evaluation shows CtxMem outperforms conventional CXL-SSD by 1.4x in execution time and doubles system throughput, demonstrating efficient large-scale memory expansion.

Quantum Error Correction (QEC) demands efficient implementation of syndrome extraction circuits. However, existing compilers for neutral-atom processors largely miss the opportunity to co-optimize these circuits by exploiting both the structural properties of Quantum Error-Correcting Codes (QECCs) and the physical constraints of neutral-atom architectures. In this work, we introduce NEAT, an SMT-based compiler that jointly optimizes qubit mapping and syndrome extraction scheduling for a broad class of stabilizer-based QECCs, achieving depth-optimal execution with minimal shuttling overhead on neutral-atom platforms. Across a wide range of QECCs, NEAT consistently achieves near-optimal circuit depth and reduces atom movement by 3×–30× compared the baseline compiler Enola. Logical-level simulations further demonstrate 2×–20× lower logical error rates under realistic hardware noise. A hierarchical symmetry-breaking formulation and relaxed parallel-motion constraints substantially improve solver scalability, yielding up to 100× speedup in compilation time. Together, these results show that NEAT produces depth-optimal, movement-efficient, and logically robust syndrome extraction schedules, while scaling effectively to large QECCs on neutral-atom hardware.

The Performance Monitoring Unit (PMU) is a significant hardware module of modern processors. Previous studies have disclosed numerous hidden PMU events. However, their underlying microarchitectural semantics remain unexplored, which largely limits their utilization. This paper proposes a reverse engineering framework for deeply understanding the microarchitectural semantics of hidden PMU events. For demonstration, we successfully utilize the framework to reveal microarchitectural behaviors of branch-related events and discover a hidden pattern of UMask Combination in Intel CPUs. Based on the reverse-engineering results, we implement a PMU-based covert channel for Spectre-v1 in SGX and enable a high-precision website fingerprinting attack under resource-constrained conditions.

Logic optimization is a crucial step in digital circuit synthesis, directly impacting the final power, performance, and area (PPA) of integrated circuits. While reinforcement learning (RL) has shown promise in generating high-quality optimization flows, its limited generalization ability necessitates retraining for each new circuit, hindering practical deployment. To address this, we propose a novel RL-based framework that achieves strong zero-shot generalization across unseen circuits. Our work introduces three key innovations: (1) logic cone extraction to reduce input complexity and enable efficient reward estimation; (2) a cut-weighting mechanism that models global timing effects from local subgraphs; and (3) the integration of Policy Similarity Metric (PSM) to enhance state representation and improve zero-shot transfer. Evaluated on a set of unseen benchmark circuits, Our work outperforms state-of-the-art methods—achieving 31.7% lower worst negative slack (WNS) and 32.5% lower total negative slack (TNS)—while running in only 13% of the time required by prior approaches. This work demonstrates that generalizable RL can enable fast, high-quality logic optimization without circuit-specific retraining.

The prevailing surrogate-guided paradigm for CPU design space exploration (DSE) suffers from a fundamental credit assignment problem, leading to high sample complexity. This work introduces GenDSE, which reformulates DSE as a sequential decision process. Its contributions are: (1) A Markov decision process that decomposes design configuration generation into context-dependent steps. (2) A GFlowNet-based configuration generator for implicit credit assignment, linking individual decisions to final outcomes. (3) Progressive Sketching, a training paradigm to overcome GFlowNet's data hunger. Experiments show GenDSE reduces simulation costs by 90% on average while achieving superior solution quality.

Quantum circuit optimization is a key step toward the efficient execution of quantum algorithms. Template matching has emerged as one of the dominant approaches for simplifying quantum circuits, yet it confronts the intrinsic challenge of accommodating gate commutativity. The state-of-the-art template-matching algorithm relies on a directed acyclic graph (DAG) representation. While this DAG-based technique handles gate commutativity satisfactorily, it fails to preserve the local connectivity inherent to quantum circuits, thereby leading to relatively high matching complexity. In this paper, we introduce a hypergraph representation (HG), a commutativity-aware representation that collapses commuting gates into a single super-node while retaining all local connectivity. This enables matches to be extended locally without revisiting the rest of the circuit, with incremental updates limited to the immediate neighborhood. Experimental results demonstrate that our HG matcher achieves 11--606x speed-up over the DAG-based implementation in Qiskit (Iten et al., 2022) on both random and arithmetic benchmarks, while maintaining the same optimization quality. The acceleration increases with circuit size, confirming that preserving locality and connectivity is the key to scalable quantum circuit optimisation.

Deploying MoEs for multi-user inference demands low latency with tight cost. MoE acceleration strategies cache and prefetch experts, assuming temporal locality and predictable routing. When these fail, wrong experts inflate latency, enabling DoS. We expose this vulnerability in GPU-centric MoE offloading and present Icarus, a gradient-based universal attack injecting an adversarial prefix embedding to disable such acceleration. Icarus combines Temporal-Locality Minimization and Expert-Prefetch Misleading to perturb decoding, plus a scheduler balancing targets with active exploration. Across models/devices, Icarus raises cache replacements by 85.4%, cuts prefetch accuracy by 12.5%, slows decoding to 0.7×, and drives outputs to maximum length.

The deceleration of Moore's Law, combined with the rising computational demands of big-data applications and generative AI, is accelerating the development of scale-up systems. Unlike traditional scale-out architectures, scale-up systems typically extend shared memory across multiple nodes using high-bandwidth, load/store-based interconnects such as CXL, UALink, NVLink, and Unified-Bus. Designing and optimizing such interconnected systems poses a multi-faceted challenge spanning computer architecture, interconnect technology and software system. Although industry has introduced numerous commercial solutions, the academic community still lacks an open-source, hardware-based platform to support cross-stack research, such as exploring new protocols, topologies, I/O controller or switch architectures, and system-level software optimizations. To address such a huge gap, we introduce OpenSUN, a novel FPGA-based multi-node system that supports customizable architecture and software systems. Its baseline architecture integrates a full-stack design, encompassing I/O controllers, switches, protocol stacks, and software systems. These components are all accessible through user-friendly interfaces at each layer to enable agile prototyping of novel hardware and software designs. By providing this open, community-accessible platform, OpenSUN aims to foster exploration and innovation in next-generation scale-up interconnect systems.

High-accuracy thermal simulation is essential for modern 3D integrated circuits (ICs), but its high computational cost often hinders early-stage, thermal-aware design. To address this, we propose FLASH3D, a fast and versatile analytical simulator for 3D steady-state thermal analysis. FLASH3D integrates spectral modal decomposition, the transfer matrix method, and an accelerated power decomposition algorithm to compute 3D temperature distributions efficiently and accurately. Compared with COMSOL, FLASH3D achieves over four orders of magnitude speedup, reducing computation time from minutes to milliseconds while maintaining a maximum absolute error below 0.5 K. Compared to the state-of-the-art machine learning (ML) method DeepOHeat, within a single inference time, FLASH3D can compute the temperature distribution of roughly 2000 slices and attains approximately 10× lower error. Furthermore, FLASH3D supports complex boundary conditions and fine-grained power maps, including curved-edge and standard-cell-level distributions, overcoming the limitations of conventional analytical methods. These features make FLASH3D an efficient, reliable, and scalable tool for early-stage thermal-aware design, providing a solid foundation for thermal optimization of large-scale 3D ICs.

Spatially partitioned heterogeneous accelerators (HAs) are increasingly adopted in embedded systems for their performance and flexibility. Yet most existing HA design frameworks optimize primarily for throughput or quality-of-service (QoS) metrics, they often overlook safety-critical real-time requirements, including hardware support for predictable execution, real-time-aware design space exploration (DSE), and rigorous schedulability analy- sis. These requirements are essential in safety-critical applications such as smart transportation, where timing guarantees directly affect system safety. To address this gap, we present PHAROS, a real-time-centric HA design framework. PHAROS introduces preemption mechanisms and scheduler designs for spatially partitioned HAs under FIFO and earliest-deadline-first (EDF) policies. Leveraging modern real-time theory, we further develop a soft real-time (SRT) schedulability-oriented DSE with objectives and constraints tailored to timing correctness. Through comprehensive modeling, analysis, and evaluation across diverse applications, we show that PHAROS's schedulability-oriented DSE discovers more feasible configurations for a broader range of task sets than throughput-oriented DSE baselines, while delivering improved real-time performance. We also provide response-time analyses for the supported scheduling algorithms.

Design Rule Checking (DRC) is a critical yet computation-intensive stage in modern very large scale integration design. As processes evolve, the high computational cost of DRC has become a significant bottleneck for design efficiency. Current acceleration approaches do not fully leverage the parallelism of DRC, resulting in limited performance gains. To address this challenge, we propose AccDRC, an FPGA-accelerated DRC based on software–hardware co-design. On the software, we design a cell-aware partitioning strategy with a data preparation and task encapsulation mechanism, which reorganize layouts into balanced task units tailored for FPGA processing. On the hardware, we implements an acceleration architecture consisting of a locality-preserving data-loading module, a unified and reconfigurable check core, and a sparse result writeback module. This architecture exploits DRC's locality, structural commonality across rules, and sparse violation outcomes, enabling high-throughput dataflow execution with multi-level parallelism. Experimental results show that AccDRC achieves 522.11x ~1071.03x speedup over the CPU-based DRC tool KLayout, and 9.62x ~ 26.07 x speedup over the state-of-the-art GPU-based DRC tool OpenDRC.

We propose KEEP, a KV-cache-centric memory management system for efficient embodied planning. To reduce cache invalidation caused by memory updates, we propose Static-Dynamic Memory Construction, which groups memory by update frequency and manages memory at different granularities. To reduce the impact of cross-attention ignorance between different groups, we propose Multi-hop Memory Re-computation, which dynamically identifies and recovers critical memory interactions through iterative memory importance propagation. We also propose Layer-balanced Memory Loading, a scheduling strategy that eliminates unbalanced KV loading and computation overhead between different layers caused by KV recomputation.

With the rapid growths of generative models like diffusion models (DMs), distinguishing authentic images from forfeited ones has become increasingly challenging, raising privacy, security, and ethical concerns. Watermarking offers an effective solution for authentication and traceability of generated images. Unlike traditional methods, emerging watermarking techniques for DMs enable marking AI-generated content with resilience to commonly used watermark weakening or erasing techniques. However, these methods demand high computational resource and latency, posing challenges for practical use, especially on edge devices.This work presents DM-MARK, a software-hardware co-optimized diffusion framework supporting efficient watermark generation and reverse detection. DM-MARK is implemented in 12nm FinFET technology, achieving robust watermarking with improved quality and reduced overhead. Evaluations show 11.33% higher detection accuracy, 18× latency speedup over GPU, 3.1× on-chip memory savings, an average of 4.56× EMA reduction. It also achieves 212.5× speedup over the baseline ASIC design with negligible accuracy loss. The proposed DM-MARK scheme offers a scalable and practical solution for protecting AI-generated content in real-time on edge devices.

Minkowski distance metrics (Lₚ) are widely used in AI. For hardware, digital designs incur limited parallelism and high energy/latency. Alternatively, content addressable memory (CAM) supports large-scale parallel distance metrics. However, existing CAM-based designs mainly support L₀/L₁, with limited scalability/configurability. In this work, we propose a segmented thermometer-encoded multibit CAM (STEM-CAM) architecture, enabling arbitrary-order Lₚ metrics. Segmenting distance norms with wildcard-augmented thermometer encoding, STEM-CAM enables a structured, scalable encoding for Lₚ. Moreover, an ultra-compact FeFET-based encoding-aware multibit CAM cell is proposed, providing efficient, high-precision implementation. Experiments demonstrate high throughput and area/energy efficiency for Lₚ, showing great potential for distance-based AI.

3D Gaussian Splatting (3DGS) has emerged as the state-of-the-art (SOTA) technique for novel view synthesis. This paper introduces an algorithm that employs a two-stage pipeline. First, a 2D Gaussian (2DGS) model is rendered via the nearest Gaussian's color. Subsequently, this depth map is utilized for the second stage: a sort-free, weighted rendering of the complete 3DGS model. We further propose CODA, a unified hardware accelerator co-optimized to execute this 2D-3D hybrid pipeline. Experimental results demonstrate that CODA exhibits an 8.4× to 11.6× speedup over the NVIDIA RTX 3060M and a 2.7× to 3.9× speedup over the NVIDIA RTX 4090.

Computing-in-Memory (CIM) is a promising solution to the memory wall, yet most prior studies optimize only one level—macro, accelerator, or architecture—rather than the full stack. This work presents HYPER-CIM, a hierarchical predictive exploration and realizable design flow that integrates all three levels. We build a scalable, fully digital CIM template in 28 nm with tunable accumulation length, local storage length, precision, parallel channels, and pipeline depth. More than 8k silicon-consistent design points were used to train a multi-head hierarchical circuit-optimization (MHCO) surrogate model, which predicts power, performance, and area (PPA) across 297M configurations. The resulting CIM "white-box" model offers circuit-faithful visibility for architecture-level design-space exploration (DSE) and Pareto search. Guided by this flow, we fabricated and silicon-verified four processing-element (PE)-flow CIM macros and one cross-level-flow CIM (CF-CIM) macro in 28 nm CMOS technology. Based on chip test results, the best-performing macro achieves 90.8 TOPS/W and 1.23 TOPS/mm², yielding a figure-of-merit (FoM) improvement of 31.12×–3.8×10⁶× over prior CIM designs. Under identical specifications, the CF-CIM improves energy efficiency from 52.13 TOPS/W to 67.9 TOPS/W and area efficiency from 0.41 TOPS/mm² to 0.51 TOPS/mm².

High-Level Synthesis (HLS) plays a pivotal role in AI accelerator design, but significant challenges remain in achieving full automation, particularly in areas like module partitioning, dataflow orchestration, and throughput maximization. Current solutions, such as compiler-based optimizations and large language models (LLMs), face limitations in adaptability, system-level optimization, and handling complex computational models. We propose a novel LLM-powered framework that automates the generation and optimization of system-level HLS architectures. The framework generates modular dataflow architectures, refines them through pattern-based optimizations, and produces synthesizable hardware implementations, demonstrating an average performance improvement of 11.78× over current SOTA approaches.

Near-memory processing (NMP) is a promising way to overcome the memory wall in large language models (LLMs). However, dataflow optimization in NMP is fundamentally constrained, as existing analyses cannot efficiently handle the new distributed vault/channel organization. We propose the Remote-Access-Free (RAF) dataflow, which uses tensor rotation to abstract this distributed organization and eliminate all intra-operator remote access. On top of RAF, we apply analytical optimization to minimize intra-operator local access, thereby achieving the intra-operator communication lower bound. We then introduce data partitioning that removes inter-operator remote access and enable operator fusion to minimize inter-operator local access, so that the inter-operator communication lower bound is also reached. Experimental results show that RAF reduces energy by 50.4%, 39.0%, and 37.8%, and delivers speedups of 3.98×, 1.72×, and 1.57× over IANUS, H^2LLM, and OptiPIM, respectively.

Solid-State Drives (SSDs) now power data centers, high-performance computing, and artifical intelligence workloads, but the increasing complexity of modern SSD controllers has surpassed the capabilities of traditional rule-based verification, necessitating scalable, data-driven testing methods. In this paper, we present ARTEMIS, a reinforcement‑learning (RL)‑based framework for automatic SSD test case (TC) generation that operates directly on commercial devices. Our contributions are threefold. First, we formulate a novel RL problem, enabling seamless deployment across heterogeneous commercial products without requiring any device-specific customization. Second, to cope with the highly dynamic and non‑stationary operating environments of SSDs, we introduce an ensemble‑based inference mechanism that aggregates policies learned under diverse workload distributions, thereby improving generalization and robustness. Third, we validate the approach on two representative stress‑testing tasks: Meta and User Garbage Collection. We show that the RL‑driven tester discovers high-impact TCs that trigger critical blocking garbage collection events more frequently than conventional methods in diverse tasks.

BFP is emerging as an attractive data format for edge NPUs, combining wide dynamic range with high hardware efficiency. However, its behavior under hardware faults and its suitability for safety-critical deployments remain largely underexplored. Here, we present the first in-depth empirical reliability study of BFP-based NPUs. Using RTL-level fault injection on NPUs, our bit- and path-level analysis reveals pronounced heterogeneous vulnerabilities and shows that the conventional end-to-end check becomes largely ineffective under nonlinear block scaling. Guided by these insights, we design a fault-tolerant BFP-based NPU microarchitecture that aligns the BFP computational semantics with reliability constraints. The design uses a row/column-wise blocking strategy to decouple the fixed-point mantissa computations from the scalar exponent path, and introduces ultra-lightweight protection mechanisms for each. Experimental results demonstrate that our design achieves near–dual modular redundancy reliability with only 3.55% geometric mean performance overhead and less than 2% hardware cost.

Analog in-Pixel computing (IPC) enables energy-efficient edge AI but faces critical noise challenges limiting computing accuracy. Existing design flows lack comprehensive device-aware noise modeling and cross-layer optimization. We introduce NoiseXplore, the first end-to-end design-technology co-optimization framework integrating: (1) physics-grounded noise models (thermal, shot, RTN, device mismatch); (2) device-aware SNR estimation and neural network co-simulation; (3) circuit-level performance modeling integrated into NeuroSim; and (4) automated Bayesian DTCO for multidimensional design space exploration. Demonstrated on noise-sensitive 1T FDSOI-based IPC, optimized configurations achieve 50 fps with 86.8% CIFAR-10 classification accuracy on a three-class subset (airplane/car/ship).

Technology Computer-Aided Design (TCAD) solves coupled partial differential equations (PDEs) to obtain spatially resolved physical fields that are essential for comprehending device behavior. However, the computationally intensive numerical solution procedures in traditional TCAD make the iterative simulation-optimization loop prohibitively costly. Existing machine learning surrogates typically regress scalar metrics directly from device conditions, consequently discarding the field-level physical information crucial for further analysis. To address this challenge, we propose FUSE-TCAD, a diffusion-based surrogate that generates the joint distribution of physical fields while supporting continuous control over geometry and bias through conditional injection mechanisms. By leveraging the probabilistic generative formulation of diffusion models, FUSE-TCAD captures the underlying statistics of coupled physical fields and preserves cross-field consistency, thereby achieving highly accurate field predictions across diverse device conditions. A physics-aware Sobolev-edge regularization strategy enforces gradient consistency to ensure high fidelity in junction regions during sampling. On SOI-FET datasets, FUSE-TCAD demonstrates robust transferability and produces high-fidelity fields using only 20% target-domain data through efficient transfer learning. Extensive experiments demonstrate that FUSE-TCAD achieves more than 30× speedup over commercial TCAD tools and maintains relative error within 0.8%, thereby supporting scalable, near-real-time device design exploration.

This paper presents an Elegant Scan Chain Activity Probability Establishment (ESCAPE) architecture for programmable low power LBIST. In the designed low-power control circuit, a programmable probability generator periodically outputs a user-configurable sequence of probabilities to drive hold registers. A 2D AND-gate array formed by two groups of hold registers then produces a rich set of low-power control signals. By modulating the enable probability of the lockups situated before the phase shifter, ESCAPE achieves precise per-chain power management. Experimental results on industrial-scale designs demonstrate that, the proposed method achieves high coverage, while reducing peak power consumption and incurring lower hardware overhead.

Weight quantization enables efficient LLM inference but requires mixed-precision computation (e.g., FP16xINT4), which is not efficient in general-purpose processors. Existing accelerators integrate custom mixed-precision arithmetic units but follow the dot-product paradigm, which suffers from numerous multiplications. This work exploits multiplication fusion in low-bit quantization and introduces MFDP, a novel dot-product paradigm that fuses identical-weight multiplications into a single operation. Based on MFDP, we propose FuseDot, an accelerator that optimizes the fusion process by incorporating index-driven generalized matrix multiplication and a hierarchical dual-phase reordering algorithm. Additionally, a cross-PE multiplier-sharing architecture with a half-multiplier scheme further amortizes multiplier costs across multiple PEs. This work achieves 1.51–1.98x speedup and 1.19–1.51x higher energy efficiency over state-of-the-art accelerators.

Fracturable LUTs (FLUTs) creates variable logic consumption for LUT implementations since two LUTs can be merged to one FLUT under certain constraints. Traditional technology mapping algorithms fail to exploit this feature due to their static-cost area models. To bridge this gap, we introduce merging probability, a quantitative, mapping-stage metric that predicts the likelihood of LUT merging during the subsequent packing phase. Based on this, we present a dynamic-cost LUT area model, enabling area recovery better suited for FLUTs. Experimental results on EPFL benchmarks demonstrate that our method reduces the usage of FLUTs by at most of 10.3% on mainstream commercial FPGAs, compared to the state-of-the-art technology mapping algorithm, without any performance degradation.

Binary neural networks (BNNs) have emerged as promising models for lightweight intelligent inference by binarizing inputs and weights. Compute in memory (CIM) architectures, which reduce data movements through in-situ operations, have become a strong candidate for BNN accelerators. However, prior works often overlook the security of the model, leaving BNN weights exposed in memory cells and vulnerable to threats such as cloning, tampering, and reverse engineering. This work proposes CPA-BNN, a secure BNN CIM architecture based on resistive random access memory (RRAM). We propose a 4T2R RRAM cell design which implements in-situ encryption and ciphertext convolution operations to protect the weights. In addition, an in-memory batch normalization (BN) scheme is proposed to optimize area overhead and improve compute density. Besides, we propose an intrinsic physical unclonable function (PUF) entropy extraction method and a current tilt-based masking stratege, enabling reliable key extraction within a unified array. The results show that CPA-BNN achieves ~100% key reliability and effectively prevents model attacks. Compared to state-of-the-art SRAM/NVM BNN schemes, CPA-BNN achieves >1.4× compute density and >1.6× storage density improvement.

Design space exploration for microarchitecture parameters is a critical aspect of processor design, requiring a balance between evaluation cost and accuracy. New designs can be evaluated using either coarse-grained simulation (high efficiency, low accuracy) or fine-grained simulation (low efficiency, high accuracy). To address this efficiency-accuracy tradeoff, we propose XSearch, which employs multi-fidelity Bayesian optimization by cross-evaluating across simulators with varying fidelity levels. This approach leverages the efficiency of low-fidelity simulations to explore more design points while ensuring accuracy through calibration using high-fidelity simulation data. XSearch has been successfully applied to explore the design space of the large-scale open-source high-performance processor core XiangShan.

RNS-CKKS is a fully homomorphic encryption scheme supporting fixed-point arithmetic, widely used in privacy-preserving convolutional neural network (CNN) inference. However, its significant computational overhead, especially from bootstrapping—the most costly operation—raises deployment costs for CNN inference over RNS-CKKS. While sparsity has proven effective in reducing computational overhead for unencrypted CNN inference, its application to large datasets (e.g., ImageNet) with RNS-CKKS-based CNN inference remains under-explored, particularly in optimizing bootstrapping operations that dominate computation time. In this work, we observe that sparsity in CNN can be exploited to reduce the bootstrapping overhead in RNS-CKKS-based CNN inference. Based on this observation, we propose FBS, a framework that accelerates CNN inference over RNS-CKKS by leveraging Fewer Bootstrapping Sparsity to reduce bootstrapping costs. We propose two sparsity patterns: eliminate missing input sparsity pattern and channel sparsity pattern, to reduce the number of bootstrapping calls during CNN inference. An iterative latency optimization framework is then presented to identify the key layers for pruning and determine the sparsity patterns to achieve effective performance. Results show that FBS can accelerate CNN inference over RNS-CKKS by up to 1.91 times with negligible accuracy loss. FBS will be open-sourced.

Dynamic-iterative aggregation (DIA) in graph neural networks updates node states sequentially and asynchronously. This expands the receptive field without adding layers and improves accuracy-per-operation versus layer-synchronous models. However, DIA introduces fine-grained serial dependencies and highly irregular sparse traffic that undermine conventional SIMD/accelerator designs. We present DIA-CIM, a 28-nm compute-in-memory (CIM) macro co-designed for DIA. DIA-CIM employs a CSR-driven, output-stationary dataflow to keep partial sums local while streaming edges, a sparsity-priority BF16 pipeline that exploits bit/value sparsity. Fabricated in 28-nm CMOS, DIA-CIM reaches 60.01 TFLOPS/W. On representative DIA workloads, it delivers >3.56 × lower energy and >2.32 × lower latency.

As integrated circuit (IC) designs grow increasingly complex and transistor counts per chip exceed ten billion, post-layout SPICE simulations involve large-scale sparse linear systems, severely degrading simulation efficiency Current GPU acceleration methods, despite their promise, struggle with efficient load balancing and resource utilization, which restricts their effectiveness in ultra-large-scale circuit simulations. In this paper, we propose a levelized load-balanced and structure-adaptive LU factorization framework for GPU-based circuit simulation. Our method improves resource utilization and parallel efficiency by introducing computation-balanced dependency level partitioning, adaptive resource allocation, and a hybrid matrix indexing mechanism. These strategies ensure that both the memory and computational resources of the GPU are fully leveraged. We demonstrate significant acceleration over existing methods, achieving a 2.1X speedup compared to GLU3.0 and a 5.2X speedup over 16-thread PARDISO on circuit sparse matrices ranging from thousands to millions of dimensions. Additionally, our framework has been successfully integrated into the open-source SPICE simulator Ngspice, accelerating circuit simulations with promising results and showcasing its potential for large-scale IC design verification.

High-accuracy qubit-state readout is critical for quantum computation. While existing hardware-based qubit-state discriminators assume stable readout statistics across measurement shots, realistic long-running tasks like chemistry simulation suffer from slow noise fluctuations and drift that severely degrade fidelity over time. We present NIAQ, an adaptive software–hardware co-design combining Kalman filtering for drift tracking with MLP discriminators for robustness against noise, together with degradation rate (%/hour) as a novel metric to quantify long-term stability. NIAQ achieves 88% qubit-state-readout accuracy in multi-qubit dataset that is equivalent to 1-day runtime, compared to the 61% baseline qubit-state discriminator, and yields 19× lower degradation rate. Optimized for low-power real-time operation on ASIC, post-synthesis results in 28-nm CMOS show 148mW power and 5ns delay, achieving 7.7× power and 6.4× latency improvements compared to the state-of-the-art.

In recent years, DeepSeek has achieved strong inference performance but remains hard to deploy on energy-constrained edge devices. This paper presents the DeepSeek Processing Element (DSPE), an edge-oriented architecture that alleviates the model's heavy computational and energy demands. DSPE introduces three techniques: the MerkleTree-based Incremental Pruning Scheme (MIPS) for secure redundant-vector reduction, the Multi-Stage Boothing Lookup Method (MBLM) for bit-flip–aware approximate multiplication, and the Dynamic Adaptive Posit Processing Mechanism (DAPPM), which introduces a new DA-Posit format and its corresponding hardware multiplication architecture. Implemented in TSMC 28nm CMOS, DSPE achieves 91.7 TFLOPS/W energy efficiency compared with state-of-the-art designs and offers a scalable foundation for edge deployment.

Clock Tree Synthesis (CTS) constitutes a complex, discrete, and combinatorial multi-objective optimization (MOO) problem, which is typically fragmented into sequential steps, including clustering, topology generation, and buffering in traditional flows, leading to suboptimal results due to local optima. Despite significant potential in MOO, differentiable methods are inherently limited to represent dynamic topological adjustments during CTS. To solve this, We propose an end-to-end differentiable CTS framework, DCTS, based on Probabilistic Graphical Model (PGM) to re-parameterize the discrete topological search into a continuous gradient-based problem, enabling co-optimization of clock tree topology and buffer sizing within a global design space. The proposed DCTS was evaluated on ISCAS'89 and OpenCores benchmark circuits under the ASAP7 technology node. Experimental results show that it achieves competitive power, performance, and area (PPA) metrics against a leading commercial tool, along with a 2.78$\times$ speedup on large-scale circuits. Furthermore, when compared to state-of-the-art academic solutions, DCTS guarantees minimum improvements of 20\% in delay, 17\% in skew, 1\% in power, and 17\% in area, while also achieving a minimum speedup of 1.98$\times$ on large-scale designs.

As capacitance extraction accuracy of rule-based pattern matching becomes difficult to sustain at advanced nodes, a growing trend emerges to develop deep-learning-based 2D capacitance models. However, existing MLP- and CNN-based methods constrain their input to fixed metal-layer combinations in a specific process node, limiting their usability in practice. Recognizing the inherent similarity between capacitance matrix and the prevailing attention mechanism, we propose AttentionCap, a customized Transformer for capacitance matrix learning, with a Gram representation framework, a physics-aligned symmetric-attention output layer, and a novel normalized Laplacian loss. We also introduce a process-node embedding to enable multi-node learning. Trained on synthetic data, AttentionCap attains 0.67%/3.99% self/coupling-capacitance error on unseen real designs under a multi-layer and multi-node setting, surpassing the CNN-Cap baseline with 4.6x/5.7x lower self/coupling error and 192x faster inference speed. A pretrained AttentionCap accurately transfers to an unseen node with only 5K samples and 4K finetuning steps. With sufficient accuracy on unseen real designs and strong transferability to new process nodes, AttentionCap offers highly practical value for modern EDA workflows. Code and data are available at https://anonymous.4open.science/r/AttentionCap-release-F698.

We present CapBench, a fully reproducible, multi-PDK dataset for capacitance extraction. The dataset is derived from open-source designs, including single-core CPUs, Systems-on-Chip, and media accelerators. All designs are fully placed and routed using 14 independent OpenROAD flow runs spanning three technology nodes: ASAP7, NanGate45, and Sky130HD. From these layouts, we extract 61,855 3D windows across three size tiers to enable transfer learning and scalability studies. High-fidelity capacitance labels are generated using RWCap, a state-of-the-art random-walk solver, and validated against the industry-standard Raphael, achieving a mean absolute error of 0.64% for total capacitance. Each window is pre-processed into density maps, graph representations, and point clouds. We evaluate 10 machine learning architectures that illustrate dataset usage and serve as baselines, including convolutional neural networks (CNNs), point cloud transformers, and graph neural networks (GNNs). CNNs demonstrate the lowest errors (1.75%), while GNNs are up to 41.4 times faster but exhibit the larger errors (10.2%), illustrating a clear accuracy–speed trade-off.

UAV trajectory tracking demands robustness and real-time performance, but traditional architectures suffer high latency, failing to counter sudden disturbances. We propose an algorithm-hardware co-design framework to address this. We integrate reinforcement learning (RL) with model predictive control (MPC) for real-time online learning. Hardware-wise, we designed a dedicated analog compute-in-memory (ACIM) accelerator, RM-CIMA, mapping both RL learning and MPC optimization to the analog domain. RM-CIMA enables UAVs to counter fast disturbances, improving recovery times from strong wind by 7.9× over traditional NMPC. Furthermore, it reduces computational latency and energy consumption by 2995.6× and 983.1×, respectively, compared to traditional architectures.

Abstract Graph Convolutional Networks (GCNs), a foundational technology for relational data applications, are often bottlenecked by irregular memory accesses caused by sparse graph structures. Existing accelerators face two fundamental limitations: their rigid dataflows cannot adapt to varying graph sparsities, and their narrow focus on high-degree nodes (HDNs) leads to systematic neglect of memory traffic from the vast number of low-degree nodes (LDNs). To address these issues, this paper introduces BSGCN, an accelerator built on a novel band-segmentation strategy. This approach partitions the graph such that the majority of LDNs are grouped into large bands with similar data reuse characteristics, while the remaining nodes form small bands containing only a few LDNs. This segregation enables two co-designed innovations: 1) a Band-Segmented Dataflow (BSD), which applies a tailored traversal strategy to each band type to handle diverse sparsity patterns, and 2) a Band-Segmented Caching (BSC) hierarchy, combining a specialized caching policy to exploit the reuse potential of LDNs with a dedicated pinning mechanism for HDNs. Evaluation results show that BSGCN achieves average speedups of 1.41× (up to 4.80×) over state-of-the-art accelerators, while reducing DRAM traffic by 24.24% and improving energy efficiency by 1.30×.

Sparse-dense matrix multiplication (SpMM) is a core component in many critical applications such as deep learning and scientific computing. Existing SpMM accelerators employ the COO format to compress sparse matrices and rely on high-bandwidth off-chip memory for performance gains. However, four major challenges remain unaddressed: 1) Fixed 2-D partitioning strategies lead to workload imbalance among processing nodes due to irregular distribution of non-zero elements in sparse matrices. 2) Redundant metadata from the COO format results in a communication bottleneck that hinders the scalability of existing SpMM accelerators. 3) To accommodate irregular memory access patterns, the use of multiple data replicas significantly increases the pressure on on-chip storage resources. 4) Handling RAW hazards from floating-point adders in software incurs substantial pre-processing overhead. To address these challenges, we propose DAP, the first 2-D multi-chip-based architecture composed of dedicated accelerators, and SPU, a novel communication-friendly SpMM accelerator. To mitigate load imbalance caused by irregular non-zero distribution, we design a two-level matrix partitioning framework that effectively balances workloads across nodes in a 2-D computing array, achieving a performance improvement of 1.43x. Furthermore, the SPU adopts CSC over COO format to reduce communication traffic. SPU also minimizes redundant on-chip storage from data replication, with only a 0.067x performance penalty due to memory access conflicts. By employing a reservation buffer, the SPU resolves RAW dependencies without time-consuming pre-processing. Our simulation-based evaluation demonstrates DAP achieves geometric mean throughputs of 2.69x relative to NVIDIA A100 GPU at 500MHz frequency.

Deploying DNNs on System-on-Chips (SoC) with multiple heterogeneous acceleration engines is challenging, and the majority of deployment frameworks cannot fully exploit heterogeneity. We present MATCHA, a unified DNN deployment framework that generates highly concurrent schedules for parallel, heterogeneous accelerators and uses constraint programming to optimize L3/L2 memory allocation and scheduling. Using pattern matching, tiling, and mapping across individual HW units enables parallel execution and high accelerator utilization. On the MLPerf Tiny benchmark, using a SoC with two heterogeneous accelerators, MATCHA improves accelerator utilization and reduces inference latency by up to 35% with respect to the the state-of-the-art MATCH compiler.

Despite decades of success, CMOS technology is increasingly constrained by power dissipation and propagation delay, thus motivating the exploration of photonic integrated circuits as an alternative for high-speed, energy-efficient computing. However, existing optical logic synthesis frameworks rely on an oversimplified efficiency factor model that fails to accurately capture physical attenuation and the hierarchical nature of signal degradation. This work presents Bident, a comprehensive optical logic synthesis framework that provides a physically accurate loss model and achieves optimal combiner configuration. We introduce the binary aggregate model, which explicitly reflects the binary-tree topology and input ordering in multi-input combiners. Based on this model, the Huffman tree optimization guarantees optimal Y-branch combiner configuration without requiring additional hardware resources. Meanwhile, a greedy algorithm optimally employs directional couplers at the leaf layer of a binarycombiner tree to achieve harmonic-mean efficiency at minimal hardware cost. Experimental results demonstrate that Bident achieves superior signal-attenuation reduction and lower switch cost than state-of-the-art methods, using both the conventional efficiency factor model and our binary aggregate model. A schematic-level optical circuit simulation further validates the feasibility and effectiveness of our binary-combiner configurations.

RowHammer is one of the most critical security threats in modern DRAM. The industry has introduced Per-Row Activation Counting (PRAC) to monitor activations, but this approach degrades performance by lengthening critical DRAM timing parameters. We propose TRAC (Transparent Row Activation Counting), a lightweight monitoring architecture that eliminates these drawbacks. TRAC leverages ACT-triggered update, robust in-subarray processing, and a Linear Feedback Shift Register (LFSR)-based counter to track activations transparently, without introducing timing overhead. Circuit-level simulations and system-level evaluations demonstrate TRAC's correctness, stability, and negligible area cost, establishing it as a practical and scalable defense against RowHammer.

Source Mask Optimization (SMO), as a key enabler in Design-Technology Co-Optimization (DTCO), plays a vital role in enlarging the process window (PW) for advanced technology nodes and PDK development. Conventional SMO relies heavily on iterative optimization using lithography models to obtain a single source-mask pair for improved PW. In full-chip applications, however, a set of critical patterns are co-optimized under a common source, forming a one-source-to-many-masks optimization paradigm for maximum common process window (CPW). To overcome the limitations of existing methods, we introduce CPW-SMO, a novel single-shot generative flow that simultaneously generates an optimal source and a set of corresponding mask patterns using set-based attention mechanisms. Our approach formulates the source and mask patterns as a unified set and employs a highly parallelized generative simulator to enable efficient training. By transforming multi-objective, non-differentiable CPW into a single-objective CPW preference penalty and optimizing generators through an SMO-aware gradient response method, CPW-SMO achieves nearly 2x CPW compared to state-of-the-art methods, while delivering ~200x speedup in runtime. These improvements significantly boost the practicality and effectiveness of SMO for holistic lithography applications.

Defending DNNs against bit-flip attacks (BFAs) typically incurs prohibitive computational overhead, a critical barrier for deployment in safety-critical systems. We challenge this "one-size-fits-all" defense paradigm by introducing the Weight Function Hierarchy (WFH), a framework that deconstructs DNNs into functionally distinct tiers: a compact Anchor Core for foundational representation, a Class-Sensitive layer for decision-making, and a Reservoir for redundancy. Based on WFH, our synergistic framework, WFH-BFs, couples offline preparation with online adaptation. Offline, we differentially harden the Anchor Core while embedding pruning tolerance elsewhere. Online, a lightweight integrity checker safeguards the core, while a dynamic pruning mechanism reconfigures the network to neutralize attacks. Experiments show WFH-BFs increases BFAs cost by 17.5x and maintains near-original accuracy (<1.4% drop) under high-rate random errors. Critically, our dynamic defense achieves this robust security while simultaneously reducing the overall computational load (GFLOPs), breaking the security-efficiency trade-off.

Fine-tuning Large Language Models (LLMs) has become essential for domain adaptation, but its memory-intensive property exceeds the capabilities of most GPUs. To address this challenge and democratize LLM fine-tuning, we present SlideFormer, a novel system designed for single-GPU environments. Our innovations are: (1) A lightweight asynchronous engine that treats the GPU as a sliding window and overlaps GPU computation with CPU updates and multi-tier I/O. (2) A highly efficient heterogeneous memory management scheme significantly reduces peak memory usage. (3) Optimized Triton kernels to solve key bottlenecks and integrated advanced I/O. This collaborative design enables fine-tuning of the latest 123B+ models on a single RTX 4090, supporting up to 8× larger batch sizes and 6× larger models. In evaluations, SlideFormer achieves 1.40× to 6.27× higher throughput while roughly halving CPU/GPU memory usage compared to baselines, sustaining >95% peak performance on both NVIDIA and AMD GPUs.

Inverse lithography technology (ILT) generates curvilinear masks for optimal wafer patterns and process windows. In practice, fabs employ ILT based on optical lithography (OL) models to improve wafer pattern fidelity, while mask shops perform mask data preparation (MDP) to ensure mask writability. The MDP process applies geometry-level mask process correction (MPC) guided by electron-beam lithography (EBL) simulations, followed by shot fracturing. However, this disjointed workflow, both between fabs and mask shops, as well as within MDP between MPC and shot fracturing, often results in suboptimal wafer patterns and inefficient mask preparation. This paper presents a novel, unified, end-to-end differentiable framework for co-optimizing wafer pattern fidelity and mask manufacturability. We achieve differentiability by formulating a physics-aware EBL simulator using the inherently differentiable error function (erf), which precisely captures energy deposition at the VSB shot level, enabling exact gradient computation. With OL simulation embedded in the optimization loop, the framework enables refinement of shot parameters to achieve wafer-level optimality. The proposed method unifies the workflow from fab to mask shop, aligning wafer-side lithography objectives with mask-side writability constraints within an end-to-end optimization flow, thereby improving mask manufacturability while preserving wafer pattern fidelity.

Timing-driven global placement is critical in modern VLSI physical design for achieving timing closure. Among existing approaches, weighting is a mainstream technique, but traditional weights are often manually designed based on heuristics, which can lead to suboptimal timing performance. To address this, we present an analytically-derived model of interconnect and cell-delay contributions of pin pairs along critical paths, from which we obtain explicit and differentiable formulations approximating Total Negative Slack (TNS) and Worst Negative Slack (WNS). The formulations include three wirelength components: net wirelength, linear pin-to-pin wirelength, and quadratic pin-to-pin wirelength, where net and linear pin-to-pin wirelength are smoothed via the weighted-average (WA) model. Based on these formulations, we derive a hybrid net-and-pin weighting scheme and propose a novel timing-driven global placement framework that directly optimizes TNS and WNS. The weighting scheme features dynamic and cumulative updates, ensuring that consistently critical paths are prioritized throughout optimization. Experimental results on the ICCAD'15 benchmark demonstrate that our method achieves average improvements of 39% in TNS and 6% in WNS compared with state-of-the-art timing-driven placers, while maintaining competitive wirelength and runtime, validating the effectiveness of the analytically-derived weighting framework.

The Mixture-of-Experts (MoE) models have emerged as the state-of-the-art paradigm for scaling up large language models (LLMs) without a proportional increase in computational cost. However, on-device deployment of MoE models still faces a critical challenge due to the large memory requirement for storing all expert parameters. In this work, we proposed NASiC, a 3D NAND-based CAM-selected multibit CIM architecture through algorithm-hardware co-optimization, tailored to the high-density storage and sparse computation requirements of MoE models. V-ASIC architecture achieves improved throughput, high area- and energy-efficiency, indicating its great potential for on-device MoE inference.

The problem of k-way hypergraph partitioning is fundamental with significant applications in various fields, including VLSI design and scientific computing. State-of-the-art hypergraph partitioners commonly employ a multi-level framework encompassing coarsening, initial partitioning, uncoarsening, and refinement phases. However, many existing methods do not scale well to problems requiring a large number of partitions (i.e., large k). In pursuit of exceptionally high solution quality, existing memetic approaches often execute their two key operations, recombination and mutation, by invoking separate, standalone multi-level partitioners. This design choice, however, renders them significantly more time-consuming than standard multi-level partitioners. To make such memetic approaches more practical, we propose an advanced memetic framework, IMPart, which introduces novel recombination and mutation operators and integrates them directly into the uncoarsening phase of a single multi-level framework. This transforms the local searches of different granularities in the traditional multi-level framework into a sophisticated, collaborative search. Experimental results on multiple standard benchmarks demonstrate our framework more effectively escapes local optima and explores the global solution space for higher-quality solutions, substantially outperforming all existing hypergraph partitioners for large-k-way hypergraph partitioning. Our framework highlights a new paradigm for the development of advanced hypergraph partitioners.

In semiconductor manufacturing, contour extraction from scanning electron microscope (SEM) images is essential for accurate lithographic metrology and process optimization. However, the low contrast, high noise, and complex structures of SEM images lead to blurred contours, making precise contour extraction extremely challenging. Existing methods struggle to capture detailed geometric features and fail to meet the high-precision requirements. In this paper, we propose FreqSEM, a frequency-aware contour extraction framework that achieves sub-nanometer-level precision, incorporating Fast Fourier Transform (FFT) for edge feature enhancement and Segment Anything Model 2 (SAM2) for edge localization. To exploit the characteristics of different frequency bands, we first apply FFT to extract the low- and mid-frequency components of the input image. Subsequently, the low-frequency component, which preserves the overall brightness distribution and large-scale structures, is used to generate SEM-adapted prompts for SAM2. Meanwhile, the mid-frequency component, which retains edges, textures, and other fine-scale details, is injected into the image encoder to enhance edge representation. In terms of the training strategy, to further enhance SAM2's focus on edges, we design an edge-aware loss function with a weight map emphasizing boundaries and a Sobel gradient loss. With limited training data, our method achieves an EPE mean of only 0.334 nm and a standard deviation of 0.661 nm at the minimum line width of 81 nm, significantly outperforming existing approaches.

Hypergraph partitioning is a critical step in the design of complex embedded systems, essential for optimizing task mapping on heterogeneous MPSoCs and enabling multi-FPGA prototyping. Many existing methods rely on community detection to identify modules with dense internal and sparse external connections, typically utilizing them to constrain the coarsening phase—a widely adopted paradigm. In this work, we propose ComPart, a generalized framework that integrates diverse community detection methods to uncover high-quality clusterings throughout the post-coarsening stages (i.e., initial partitioning and uncoarsening). These discovered clusterings serve as distinct structural guides, enabling the refinement process to identify superior partitioning solutions. Our framework offers two key advantages: (1) it establishes a new paradigm that leverages community structures detected during uncoarsening to escape local optima and explore globally meaningful solution subspaces, transcending the limitations of standard local refinements; and (2) it flexibly accommodates both existing and future community detection methods. Furthermore, we theoretically generalize locally-dense decomposition—originally from graphs—to the hypergraph domain. We provide the formal extension and necessary proofs to apply this technique to hypergraphs, marking its first application in hypergraph partitioning. Specifically, we utilize this rigorously derived decomposition to guide the initial partitioning phase toward superior starting points. Experimental results on standard benchmarks demonstrate that our method consistently outperforms state-of-the-art methods in solution quality.

Large Foundation Model (LFM) inference is both memory- and compute-intensive, traditionally relying on GPUs. However, their limited availability and high cost have driven growing interest in high-performance general-purpose CPUs, particularly emerging 3D-stacked Static Non-Uniform Cache Architecture (3D S-NUCA) systems. While these architectures improve bandwidth and data locality, they introduce severe thermal constraints and non-uniform cache latencies caused by 3D Networks-on-Chip (NoC). Efficient management of thread migration and V/f scaling remains challenging due to diverse LFM kernels and hardware heterogeneity. We propose AILFM, an Active Imitation Learning (AIL)–based scheduling framework that learns near-optimal thermal-aware policies from Oracle demonstrations with minimal runtime overhead. AILFM captures both core-level performance variations and kernel-specific behavior, maintaining thermal safety while maximizing inference efficiency. Extensive experiments demonstrate that AILFM outperforms state-of-the-art baselines and generalizes across diverse LFM workloads.

Masked diffusion enables region-specific image synthesis but suffers from computational redundancy, since the entire image is processed each timestep even though only the masked region requires generation. To address this, we introduce MASQ, a hardware–software co-designed accelerator for masked diffusion. Our approach performs stage-wise MXINT8/4/2 precision assignment that dynamically reflects spatial and semantic importance, complemented by timestep-aware scheduling and optimized non-matrix operations. MASQ features a block-wise multi-precision compute engine and mask management unit, efficiently handling our approach. It achieves up to 16.06x and 5.39x speedup and 4.18x and 4.93x energy-efficiency gain over A100 and Orin NX, respectively, while preserving quality.

Interpretable models like Decision Trees (DT) and Random Forests (RF) are ill-suited for edge hardware, facing von Neumann bottlenecks and sensitive to device variations. We propose a hardware-algorithm co-design, the Soft Decision Machine (SDM). Algorithmically, SDM transforms a multivariate model into a hardware-friendly univariate form. In hardware, a compact 1-FeFET analog CAM natively computes the required sigmoid function. This "soft" probabilistic approach provides inherent variation tolerance. Under 40 mV device variation, SDM maintains 93.2% accuracy on MNIST (0.54% drop), outperforming DT (43.86% drop) and RF (16.06% drop), enabling robust and efficient interpretable computing for the edge intelligence.

Quantum computing holds the potential to revolutionize numerous fields, yet the practical execution of quantum circuits depends on an efficient compilation process, including the placement of logical qubits on a quantum chip. This placement is a hard combinatorial problem that often defeats traditional heuristics and manual optimization. We present QAgent, a novel multi-agent reinforcement learning (RL) framework that autonomously optimizes logical qubit layouts on quantum processor. In QAgent, one agent is assigned to each logical qubit, and agents jointly learn placement policies that minimize circuit execution cost. To address the challenges of sparse rewards and credit assignment, we propose the Breakthrough Return Bonus (BRB), a dynamic reward shaping mechanism that encourages meaningful layout improvements and accelerates convergence. Extensive experiments on diverse quantum circuit benchmarks show that QAgent reduces execution costs by up to 53.9% compared to leading approaches, and significantly enhances circuit success rates. Ablation studies confirm that BRB is essential for stable training and effective policy optimization. These results demonstrate the promise of AI-driven, workload-aware placement for advancing fault-tolerant quantum computation.

Zoned neutral atom architectures are emerging as a promising platform for large-scale quantum computing. Their growing scale, however, creates a critical need for efficient and automated compilation solutions. Yet, existing methods fail to scale to the thousands of qubits these devices promise. State-of-the-art compilers, in particular, suffer from immense memory requirements that limit them to small-scale problems. This work proposes a scalable compilation strategy that "searches smarter, not harder". We introduce Iterative Diving Search (IDS), a goal-directed search algorithm that avoids the memory issues of previous methods, and relaxed routing, an optimization to mitigate atom rearrangement overhead. Our evaluation confirms that this approach compiles circuits with thousands of qubits and, in addition, reduces rearrangement overhead by 28.1% on average.

Incremental placement optimization improves power, performance, and area (PPA) by refining cell locations, gate sizing, and buffering under strict physical constraints. Conventional incremental flows, composed of discrete heuristic stages with isolated static timing analyses, often converge slowly and yield inconsistent PPA gains due to the lack of a unified formulation. Recent advances in differentiable placement enable gradient-based refinement on smooth surrogates of wirelength, density, and timing, offering high scalability but limited robustness near legality and timing-closure boundaries. To combine their strengths, we propose HyPAS, a hybrid optimization framework that integrates discrete sign-off optimization with differentiable gradient refinement for placement and sizing co-optimization. The discrete stage, implemented with OpenROAD, ensures legality, timing closure, and buffer-aware repair, while the differentiable stage, built on DREAMPlace, performs gradient-guided placement and sizing using a GNN-based timing-power surrogate. A Straight-Through Estimator bridges continuous gradients with discrete library parameters, enabling end-to-end physical co-optimization. Experiments show HyPAS delivers superior PPA gains with competitive runtime against 2025 ICCAD CAD Contest results and SOTA methods.

Falcon, a compact post-quantum digital signature scheme, has been selected by National Institute of Standards and Technology (NIST) for the standardization of post-quantum cryptography. While it effectively mitigates the emerging quantum threats, its susceptibly to fault attacks remains insufficiently understood. In this work, we present a novel Rowhammer-based fault attack against Falcon with only one single-bit flip, significantly reduces the number of required faulty signatures by 800× compared to the state-of-the-art attack. Our solution identifies a new vulnerable address offset in Falcon and optimizes the classical Hidden Parallelepiped Problem (HPP) attack. Our end-to-end attack on the Falcon-512 reference implementation successfully recovers the secret key with only 250k faulty signatures.

Large language models (LLMs), such as GPT-3 and Llama-2, impose extreme memory-bandwidth demands, creating severe data movement bottlenecks. Processing-in-Memory (PIM) mitigates this by performing computations near memory; however, current PCIe-based PIM systems deliver only a small fraction of their theoretical throughput. On our multi-channel PIM emulation platform, PIM cores are active for only 6.55% of execution time, primarily due to (1) serialized host–device communication that limits channel-level parallelism, (2) insufficient request-generation capability in conventional DMA engines, and (3) per-bank microarchitectures that serialize batch execution. We address these bottlenecks with a co-designed memory system and microarchitectural solution: Channel-Level Burst (CL) for autonomous per-channel operand generation, PDMA for high-throughput PIM-oriented request scheduling, and an integrated PIM core for enabling true multi-batch parallelism. Across GEMM microbenchmarks and four LLMs, CL provides 9.10x speedup, PDMA adds 29.6x, and multi-batch execution contributes 102.4x. Together, they deliver a 145.8x improvement over a baseline multi-channel PIM system, enabling PIM to surpass CPU throughput in memory-bound LLM decode kernels and approach the efficiency of GPUs.

As large language models (LLMs) are often deployed with long, context-rich prefixes, the prefix KV cache frequently exceeds GPU memory capacity. Although offloading the prefix KV cache to host memory or storage alleviates capacity pressure, it introduces severe I/O stalls that increase Time-to-First-Token (TTFT) latency. To address this challenge, we present Marlin, an I/O-efficient prefix KV cache retrieval system for long-prefix LLM inference. Marlin employs a dispersion-based token selector to precompute a compact, query-agnostic subset of important prefix tokens, and a sensitivity-guided head classifier that assigns different KV retrieval policies to classify prefix-sensitive and query-sensitive heads. An overlap-optimized attention pipeline further hides offload latency by overlapping head-specific KV transfers with attention computation. Experimental results demonstrate that Marlin significantly reduces TTFT compared to state-of-the-art methods while maintaining comparable model accuracy.

The growing demand for low-latency, high-quality video encoding in wireless applications, such as online conferencing and cloud gaming, necessitates robust screen content capabilities in mezzanine codec. However, some mezzanine codec like JPEG XS exhibit inefficiencies when handling screen content, particularly for text-rich scenes containing abundant high-frequency information. Thus we propose PEL, a low-complexity screen content enhancement layer that operates without modifying the core codec. The proposed enhancement layer is based on clustering and a palette algorithm, achieving a 18.13% BD-rate reduction on screen content datasets with 5H2V transform levels when validated with JPEG XS. The proposed method eliminates data dependencies and complex rate–distortion optimization processes, satisfying requirements for low complexity and low latency. To overcome hardware throughput bottlenecks, a scalable tri-core parallel architecture is developed for the palette algorithm. Implemented on the Xilinx ZCU106 evaluation board, the design achieves 4K@120FPS performance with only 19.7K LUTs and an additional latency of eight lines.

While ZKP hardware acceleration has focused on backend proving, we identify frontend trace generation as the new system bottleneck through system-level profiling. To address this, we propose ZK-Tracer, the first hardware accelerator architecture for the zkVM frontend. ZK-Tracer features a novel heterogeneous design couples a Main Trace Unit with parallel Permutation Trace Units, all managed by a lightweight ISA extension for efficient offloading. Our ASIC implementation shows ZK-Tracer accelerates trace generation by 1829x, delivering a remarkable 963x end-to-end system speedup. This work rebalances the ZKP system by eliminating the emerging frontend bottleneck.

The efficiency of processor-based emulation (PBE) heavily depends on the scheduling of computations. In the scheduling process, the challenge in accurate modeling time step stems from the complex instruction execution process, which is influenced by both the inter-processor communication latency, the execution sequence of the allocated nodes, and scheduling constraints. Therefore, existing works struggle with the inability to optimize the time step directly. In this paper, inspired by the key insight of the inherent connection between the time step and the topological order balancing of the netlist graph, we propose the topological order balancing-driven scheduling algorithm. Our approach introduces the mobility-prioritized node selection and efficient forward and backward propagation. Besides, a theorem is presented to reduce the time complexity of gain calculation to O(1). Experiments demonstrate significant improvements over the SOTA scheduling algorithm, achieving 72% better TOB metric, 22.5% reduction in time steps, and 55% faster runtime on public and open-source chip benchmarks, thus proving TOB as a critical metric for the scheduling process and enhancing the efficiency and performance of PBE emulation.

GPU memory management is critical for efficient Large Language Model (LLM) serving. LLM memory usage primarily comprises weights, activations, and KV caches. While weights are static, activations and KV caches exhibit dynamic and unpredictable behavior, posing significant memory management challenges. Modern LLM serving systems address this through a dual-level approach: activations inherit static tensor abstractions from deep learning frameworks, while KV caches employ specialized page-table virtualization (i.e., PagedAttention). Although this reduces KV cache fragmentation, the fundamental isolation between activation and KV cache management prevents memory sharing across these spaces, leading to suboptimal utilization and 20\% throughput degradation. To address these limitations, we propose eLLM, an elastic memory management framework. The core components of eLLM include:(1) Virtual Tensor Abstraction: Decouples the virtual address space of tensors from physical GPU memory, creating a unified and flexible memory pool;(2) Elastic Memory Mechanism: Dynamically adjusts memory allocation through runtime memory inflation and deflation, and leverages CPU memory as an extensible buffer;(3) Lightweight Scheduling Strategy: Employs Service-Level Objective (SLO)-aware policies to optimize memory utilization and effectively balance performance trade-offs under stringent SLO constraints. Comprehensive evaluations demonstrate that eLLM outperforms state-of-the-art systems, achieving up to 2.32$\times$ higher throughput.

Fault localization in modern processor design code is a critical yet time-consuming step during processor verification. While recent advances in LLM-based techniques for module-level hardware design have shown promising results, automatically localizing bugs in large-scale, project-level processor designs remains challenging. In this paper, we present BluesFL, a novel block-level LLM-based fault localization framework for processor designs. Inspired by the way engineers debug processors, we first propose a dataflow-based code blockization approach to guide LLMs to focus on critical local code context. We further propose a Block-level Instruction-Oriented Slicing (Blues) algorithm that enables LLMs to mimic human reasoning by analyzing instruction execution paths and processor states. We evaluate BluesFL on a real-world RISC-V processor core comprising 19K lines of SystemVerilog code. Experimental results demonstrate that BluesFL correctly localizes 24 bugs at Top-1, achieving 242.9% improvement over the existing state-of-the-art (7 bugs). Cost analysis shows that BluesFL requires an average of only $0.257 to localize a single bug.

Functional verification accounts for over 50% of the IC development lifecycle, making SystemVerilog Assertions (SVAs) indispensable for rigorous digital chip verification. However, manual SVA authoring is labor-intensive and error prone. To address these challenges, we introduce ChatSVA, an end-to-end SVA generation system built upon a multi-agent framework. The AgentBridge platform facilitates systematic data generation, augmentation, and validation, decomposing complex verification processes into modular, verifiable subtasks. ChatSVA achieves syntax and function pass rates of 98.66% and 96.12%, averaging 139.5 SVAs per design with 82.50% function coverage. A ChatSVA web service is publicly available.

Visual Autoregressive (VAR) model, via innovative next-resolution prediction, demonstrates significant potential of GPT-style AR models in image generation. However, due to its coarse-to-fine nature, the input token-map size grows dramatically with each step, resulting in excessive memory access and computational overhead. In this paper, we propose 3D-DuRA, an algorithm-architecture co-design based on a hybrid 3D near-memory and in-memory computing architecture equipped with dual-ring sparse attention, for efficient next-resolution visual-autoregressive generation. Experimental results demonstrate that our proposed 3D-DuRA achieves 4.1× improvement in area efficiency compared with RTX 6000 Ada GPU, along with 3.5× and 9.1× speedups and 10.1× and 13.1× improvements in energy efficiency on Infinity2B and VAR-d36, respectively.

Processing-in-Memory (PIM) alleviates the memory bottleneck of modern AI workloads; however, its limited computational capability often necessitates hybrid architectures that integrate PIM with nearby processing units. In such heterogeneous systems, communication and host-side overheads remain dominant performance bottlenecks. Our profiling of SK hynix's AiMX reveals that CPU–AiMX communication and CPU-side data reordering account for 50.07% of end-to-end LLM prefill and 78.36% of decode execution time. Notably, 54.03% of reordering operations occur adjacent to AiMX-executable nodes, indicating significant untapped potential for near-memory execution to eliminate unnecessary data movement. We propose a graph compiler that jointly optimizes computation and data movement for AiMX-based acceleration. The compiler performs (1) graph simplification to maximize AiMX-kernel coverage, (2) DMA-assisted tensor reordering and layout redefinition to offload host-side preprocessing, and (3) operator fusion to suppress redundant memory transfers. Integrated into the ONNX Runtime, our approach improves 2.00~2.73x speedup in the prefill phase and 18.50~38.29x in the decode phase, demonstrating the substantial benefits of graph-level co-optimization for PIM-enabled LLM inference and achieving performance comparable to hand-tuned AiMX execution.

Cross-component cache side-channel attacks exploit shared cache resources across different processing units to infer sensitive information, posing a significant threat to modern heterogeneous computing systems. However, the effectiveness of fine-grained cache attacks across components on Apple silicon remains unexplored. In this paper, we demonstrate that cross-component cache attacks can leak GPU sensitive information from the CPU via the System-Level Cache (SLC) on Apple M2 SoC. We first reverse-engineer the key SLC mechanisms required to enable cache attacks. Leveraging this knowledge, we introduce a GPU-to-CPU covert channel and attack targeting the Large Language Model (LLM) embedding table during local LLM inference.

Sparse tensor computation is widely used in deep learning and scientific computing, but its irregular computation and memory access patterns pose significant challenges for general-purpose accelerators such as GPUs and NPUs. FPGAs, owing to their reconfigurability, are inherently well-suited for handling sparse workloads. However, existing point-based manual design paradigms severely limit the performance potential of reconfigurable hardware across diverse sparse scenarios. To address this, we propose SpArC—an automated compilation framework for sparse tensor computation that automatically generates high-performance FPGA accelerators. SpArC consists of:(1) a primitive-based DSL serving as the design specification for sparse accelerators, providing a unified abstraction of data formats, iteration pattern, and hardware mapping strategies;(2) a two-stage mapping mechanism centered around sparse meta-operations, enabling arbitrary sparse dataflows to be efficiently mapped to hardware micro-architectures; and(3) a heuristic design space exploration method for joint software–hardware optimization.Experimental results show that SpArC can automatically generate FPGA accelerators for typical sparse workloads such as SpMSpV, Plus3, and SpMM. On the SuiteSparse benchmark dataset,for SpMSpV workloads, SpArC achieves 31.7×–130.4× performance improvement over automated frameworks such as ScaleHLS and Allo. On the same SuiteSparse SpMSpV workloads running on CPU platforms, SpArC further achieves 10.8x–34.7× speedup over TACO and 1.03x–1.89x speedup over MKL.

RISC-V has recently ratified a vector cryptography extension. Ex- haustive formal verification of hardware designs that implement this extension is crucial for security. However, scaling verification for designs with such large bit-widths is challenging. We present the first formal verification of Marian, an open-source implementa- tion of the RISC-V vector cryptography extensions. We show that proof modularization enables us to obtain an unbounded proof for Marian. Together with our systematic invariant identification, we reach an additional speedup of 174%. Our evaluation shows that invariants that assert properties of counters, such as bounds or directions, or handshakes are particularly effective in improving the verification times. We show the generalizability and reusability of our invariant identification methodology by formally verifying another custom implementation of RISC-V vector cryptography extensions. During verification, we found a violation that turned out to be a flaw in the specification, which is now being updated.

Synthetic Aperture Radar (SAR), benefiting from its all-weather, all-time, and high-resolution characteristics, has become a vital tool in earth observation. A typical application of SAR first completes the imaging process of echo data and then conducts subsequent analysis. As AI excels in image classification and recognition, integrating AI with SAR has garnered significant interest. In order to leverage the acceleration capabilities of existing AI frameworks, particularly graph optimizations, while also reducing developing complexity, developers strive to streamline the entire SAR application within these frameworks. However, a key performance challenge arises: SAR imaging differs greatly from typical AI tasks in both the requirements of data layouts and the composition of operators, causing graph optimizations to fail in effectively accelerating the SAR imaging process. The fundamental reason is the failure of the two key graph optimizations: layout transformation and operator splitting. In this paper, we first address the issue of significant transpose overhead introduced by the layout transformation strategy. To this end, we propose a novel layout transformation strategy based on pseudo-transposition operators, which can completely eliminate transpose overhead while maintaining memory access efficiency. Subsequently, we design a tailored splitting strategy based on movable reverse-order operators to compensate for existing frameworks' lack of capability in handling the core FFT operators. The proposed strategies were implemented in PyTorch and LiteRT, yielding a significant speedup of 3.45x for SAR imaging process.

Combinational equivalence checking (CEC) is a key and often time-critical step in the IC design flow for verifying functional equivalence after synthesis and technology mapping. As designs scale, improving CEC efficiency has become a major challenge with wide-ranging consequences for the entire flow. In this paper, we propose a novel parallel CEC approach through factored form sharing. In particular, the factored form literal count (FFLC) closely reflects both the amount of shareable literal/CNF-encoding and the branching complexity encountered during satisfiability (SAT)-based verification. Therefore, FFLC, together with a lightweight branching complexity proxy, guides a sharing-aware seed-and-grow partitioning algorithm that exploits literal and CNF-encoding reuse while balancing estimated SAT-solving complexity. Implemented in ABC and evaluated on large-scale benchmarks with 40 physical CPU cores, our implementation delivers geometric-mean speedups of 45.57× (max. 6,595×) over single-threaded ABC, 1.53× (max. 17×) over a state-of-the-art (SOTA) CPU-parallel method, and 5.52× (max. 382×) over a SOTA GPU-parallel method.

Safety-critical integrated circuits targeting ISO 26262 ASIL-D require a failure-in-time (FIT) $<10$. These physics-based tools for FIT prediction, such as BFIT, are accurate but slow, while ML baselines suffer collapse under long-tailed FIT distributions. We propose \textbf{ATLAS}, a decoupled GNN framework that combines a bidirectional asynchronous topological message passing backbone, aligned with BFIT's forward and backward propagation, with RankNet and CalibNet synergistic heads. RankNet uses a gap-aware pairwise ranking loss with log-gap weighting $\Delta\log(t)$ and explicit emphasis on head samples to identify top-$k\%$ high-risk gates. CalibNet employs a dual-domain loss in log and linear spaces, incorporating importance weighting, for accurate calibration. The proposed design achieves $O(|V|+|E|)$ complexity, delivering up to 220$\times$ speedup over BFIT while reducing selective hardening area overhead by 53\% compared to DeepGate2 on ITC'99 benchmarks, thereby enabling the rapid reliability-aware design of large-scale circuits. We plan to open-source our data and model code after acceptance.

Vision-Language-Action (VLA) models have emerged as a unified paradigm for robotic perception and control, enabling emergent generalization and long-horizon task execution. However, their deployment in dynamic, real-world environments is severely hindered by high inference latency. While smooth robotic interaction requires control frequencies of 20--30 Hz, current VLA models typically operate at only 3--5 Hz on edge devices due to the memory-bound nature of autoregressive decoding. Existing optimizations often require extensive retraining or compromise model accuracy. To bridge this gap, we introduce ActionFlow, a system-level inference framework tailored for resource-constrained edge platforms. At the core of ActionFlow is a Cross-Request Pipelining strategy, a novel scheduler that redefines VLA inference as a macro-pipeline of micro-requests. The strategy intelligently batches memory-bound Decode phases with compute-bound Prefill phases across continuous time steps to maximize hardware utilization. Furthermore, to support this scheduling, we propose a \textbf{Cross-Request State Packed Forward} operator and a Unified KV Ring Buffer, which fuse fragmented memory operations into efficient dense computations. Experimental results demonstrate that ActionFlow achieves a 2.55 times improvement in FPS on the OpenVLA-7B model without retraining, enabling real-time dynamic manipulation on edge hardware. Our work is available at https://anonymous.4open.science/r/ActionFlow-1D47.

Timing closure is a key objective in FPGA placement. As designs scale, heterogeneous interconnections induce strong RC effects, weakening delay–wirelength correlation and limiting existing placers with inaccurate timing models and fixed weighting. We propose LS-Placer, a learning-based, slack-aware timing-driven placement framework that jointly models net and logic delays through a graph representation and integrates the learned timing model into a dynamic global placement flow with adaptive TNS-guided weighting. On average, LS-Placer improves WNS and TNS by ~11% and ~19% and achieves 3% shorter critical path delay than Vivado 2021.2.

This work presents COmPOSER, an open-source, end-to-end framework for RF/mm-wave design automation that translates target specifications into optimized circuits with layouts. It unifies schematic synthesis, layout generation for actives and passives, and placement/routing, incorporating physics-based equations and machine-learning-driven electromagnetic models. Based on post-layout validation on multiple LNAs and PAs operating at up to 60GHz in a commercial 65nm process-kit, COmPOSER meets performance targets, comparable to expert manual designs, while delivering a 100-300x productivity gain.

Deep neural networks (DNNs) on Neural Processing Units (NPUs) require carefully optimized operator mappings to achieve high performance, yet the mapping space grows rapidly with increasingly complex on-chip memory hierarchies. Existing dataflow models rely on a computation–data coupled paradigm that forces all tensors to share identical storage structures and data transfer paths, severely limiting the expressible mapping space. We present CODA, a computation–data decoupled dataflow paradigm that enables tensor-wise independent modeling of on-chip storage and movement. CODA introduces the non-uniform loop space to jointly represent computation and per-tensor data mappings, together with an analytical performance model and a simulated-annealing–based optimizer. Across single-operator and fused-operator workloads, CODA achieves 1.10x-1.11x and 1.14x–1.85x speedup over state-of-the-art methods.

The rise of embodied intelligence is driving the deployment of Vision Transformers (ViTs) for dense prediction (DP) tasks on resource-limited edge devices. Look-up-table (LUT)-based digital compute-in-memory (CiM) has emerged as a promising paradigm, delivering high accuracy with superior energy and area efficiency. However, practical ViT deployment on LUT‑CiM for edge DP faces dual hardware and software challenges: (1) LUT cost scales exponentially with bit-width, while NLP‑oriented quantization struggles to push convolution-heavy ViTs below 8 bits, especially in compact on‑chip CiM models; and (2) fixed LUT structures cannot accommodate ViTs' heterogeneous static/dynamic workloads, while unstructured mixed‑precision weights strain memory density and utilization. To overcome these, we propose a software-hardware co-designed low-precision ViT accelerator. Software-wise, we propose Greedy G-shuffle, a lightweight, general quantization method, paired with a PCA‑based, channel‑wise weight assignment, tailored for lightweight ViTs in edge DP tasks. Hardware-wise, at the architectural level, we introduce a reconfigurable LUT-based CiM macro that accelerates both static and dynamic matrix operations with superior energy efficiency, complemented by a high-utilization pipeline- and tensor-parallel dataflow that serves heterogeneous ViT layers. At the circuit level, we employ high-density 1TnR VRRAM with flexible read paths and channel-wise hardware remapping to support mixed-precision INT4/2/1 weights, minimizing area overhead. We demonstrate the first fully 4-bit ViT with INT4 activations and structured INT4/2/1 weights on a reconfigurable 3D 1TnR VRRAM LUT-based CiM macro, achieving a 26.7% improvement in mIoU and a 30.1% reduction in RMSE on the ADE20K and NYUDv2 compared to vanilla round-to-nearest quantization, along with up to 8.9× area efficiency and 9.7× energy efficiency improvements over the state-of-the-art.

Large-scale Mixture-of-Experts (MoE) models are pivotal in modern AI, yet their massive parameter size creates a "storage wall" for fault tolerance, where limited bandwidth restricts checkpoint frequency and risks significant wasted computation. We present "EXPCheck", a dynamic expert-aware checkpointing system designed to resolve the conflict between massive MoE states and limited persistence bandwidth. Grounded in the observation that expert activation is highly imbalanced, EXPCheck employs a novel "Aging-then-Greedy Expert Selection (AGES)" policy. AGES first enforces an age-based refresh for overdue "cold" experts to prevent indefinite staleness, and then greedily allocates the remaining persistence budget to frequently updated "hot" experts. Implemented on a production-scale training stack, EXPCheck significantly reduces persistence traffic and increases checkpoint frequency by at most 5× compared to full checkpointing, while maintaining downstream model accuracy comparable to standard methods.

Deep Neural Networks (DNNs) are being deployed in safety-critical applications, where resilience to transient faults is essential. Traditional fault injection methods often face challenges in scaling efficiently to larger models, whereas the majority of existing speed-up techniques is closely linked to specific hardware or architectural configurations. To speed up the assessment of single-fault effects, an approach based on simultaneous injection of faults has demonstrated promising results, where multiple non-interacting faults are injected concurrently during a single workload execution. Nevertheless, the applicability of this method to DNNs has not been explored. In this study, we investigate the use of simultaneous injection of faults in DNNs and observe that faults can easily interact with one another due to DNNs' densely connected structure. These fault interactions can create ``artificial'' masking effects, leading to the misclassification of faults as non-critical (called false negatives), ultimately compromising the accuracy of the reliability assessment. To overcome this phenomenon, we propose an approach to mitigate the effects of such fault interaction during simultaneous injection of faults in DNNs, ensuring accurate assessment. Furthermore, we propose a strategy to further accelerate the assessment by pruning non-critical inputs from the DNN input batch during fault injection, further improving the speedup with negligible accuracy loss. To our knowledge, this is the first approach to enable accurate and efficient simultaneous injection of faults into DNNs, supporting fast reliability assessment applicable to different abstraction levels. We experiment with nearly 42 million injections at both software (SW) and RTL, achieving very low false negatives (as low as 0%, avg 0.2%) and an average injection time gain of 3.82x (RTL) and 5.29x (SW) over existing DNN fault injection approaches.

Transformer models achieve exceptional performance, but face high computational costs that hinder their deployment on resource-constrained devices. While bit-column sparsity (BCS) offers promising post-training acceleration, existing distribution-agnostic methods neglect natural sparsity in the most significant bits (MSBs) from Gaussian-like weight distributions, requiring aggressive accuracy-degrading modifications on the least significant bits (LSBs). This paper presents Duet, a bit-serial accelerator fully exploiting High-Order Lossless Sparsity in BCS for load-balanced Transformer acceleration. At the algorithm level, Distribution-Aware Pruning (DAP) partitions weights by a hyperparameter to maximize lossless MSB pruning opportunities, while Fixed Redundant Hierarchical Search (FRHS) optimally handles remaining compression, achieving 3.13/3.25 effective bits with negligible accuracy loss. At the architecture level, our Duet accelerator addresses four key challenges: (1) two-level shifter resolves bit significance mismatch in Duet encoding format; (2) parallel Metadata-Weight pipelines support variable bitwidths while completely hiding metadata processing overhead; (3) Activation Sum Generator supports time-multiplexed Metadata Pipeline; (4) dual mode operation handles both linear and attention layers in Transformer models. Duet accelerator ensures load-balanced execution for all Processing Elements (PEs). Experiments on BERT and ViT demonstrate 1.45× ~ 4.30× speedup and 1.32× ~ 2.94× energy improvement over SOTA accelerators.

Neural circuit simulators promise fast alternatives to SPICE but remain impractical due to three fundamental limitations: per-circuit hyperparameter tuning, cold-start problems from lacking crosstask knowledge sharing, and prohibitive online retraining costs that negate computational advantages. We introduce IGNITE, a pretrained neural simulator that addresses these challenges through in-context learning. Built on a self-supervised topology encoder and Prior-data Fitted Network decoder, IGNITE adapts to new circuits via a single forward pass conditioned on a small context set, eliminating online training overhead. An information-theoretic active learning strategy enables intelligent sample selection, maximizing data efficiency. IGNITE transfers knowledge across topologies and technology nodes, achieving R2 > 0.9 with only 95 samples in average—a 15.8× improvement over SOTA. Integration with optimization frameworks yields 2−30× speedup for transistor sizing and more than 5× speedup for yield optimization, demonstrating practical viability for industrial analog circuit design.

Spiking Neural Networks (SNNs) are energy-efficient and biologically plausible, ideal for embedded and security-critical systems, yet their adversarial robustness remains open. Existing adversarial attacks often overlook SNNs' bio-plausible dynamics. We propose Spike-PTSD, a biologically inspired adversarial attack framework modeled on abnormal neural firing in Post-Traumatic Stress Disorder (PTSD). It localizes decision-critical layers, selects neurons via hyper/hypoactivation signatures, and optimizes adversarial examples with dual objectives. Across six datasets, three encoding types, and four models, Spike-PTSD achieves over 99% success rates, systematically compromising SNN robustness. Code: https://anonymous.4ope- n.science/r/Anonymous-testcode.

Graphics Processing Units (GPUs) have been serving as critical computation resources for large-scale parallel computations. With increasing chip complexity, power efficiency has become an important design objective for modern GPUs. GPU power optimization relies on fast power evaluation, requiring architecture-level GPU power model. However, because of the time-consuming power label collection, only simple microbenchmarks are adopted for training. The limitation of microbenchmarks as training data incurs low accuracy for existing architecture-level GPU power models like AccelWattch. To address the limitation of microbenchmarks as training data, we propose G-Power, an architecture-level GPU power modeling framework that utilizes additional known GPU chips to provide additional knowledge. G-Power utilizes the aggregated knowledge foundation from additional known GPU chips and then performs fine-tuning on our target GPU. To provide foundations with additional known GPU chips and capture the similarity to utilize these foundations for fine-tuning, G-Power adopts a three-phase algorithm consisting of 1) pre-training with additional known chips, 2) attention-inspired aggregation, and 3) fine-tuning on our target GPU. We evaluate G-Power on four modern NVIDIA GPUs, demonstrating high accuracy. G-Power can achieve a low MAPE of 14% and a high correlation coefficient R of 0.88 on average, which are 22% lower MAPE and 0.36 higher R than AccelWattch.

Pattern matching has become one of the most predominant industrial solutions in IC design-to-manufacturing flow, with broad applications in layout verification, hotspot detection and Optical Proximity Correction (OPC). However, conventional CPU-based approaches, which rely on rule-based extraction, suffer from excessive false matches and high runtime overhead. These inefficiencies create bottlenecks in both verification and manufacturing workflows at advanced nodes. To address these limitations, we introduce the first fully GPU-accelerated pattern matching framework G-Matcher, with a novel multi-stage, multi-level architecture. Our GPU-oriented development exploits massive parallelism to process ultra large scale layout data. The multi-stage pipeline filters false matches, while the multi-level paradigm utilizes specialized pattern and layout representations to accelerate the search. On industrial datasets, our framework demonstrates a 407× speedup over the 64-thread commercial tool Calibre. On public benchmarks, it achieves 7.1× speedup over a state-of-the-art CPU implementation. Importantly, G-Matcher maintains 100% matching accuracy with zero false matches across all evaluations.

Heterogeneous Graph Neural Networks (HGNNs) are widely used to capture structural and semantic information in heterogeneous graphs based on sequences of vertex and edge types (i.e., metapaths). To support HGNNs, several solutions have been proposed and adopt a source-centric approach that can concurrently process metapath instances sharing the same source vertex. However, the vertices and edges, which are shared by different metapath instances and beyond the first hop of the same source vertex, may be repeatedly processed, incurring irregular memory accesses and redundant edge computations. In this work, we observe that HGNN inference exhibits substantial vertex and edge overlaps across metapath instances, and the metapaths sharing a common pivot vertex (i.e., the center vertex bridging multiple metapaths) exhibit strong spatial similarity that effectively captures these overlaps. Based on these observations, we propose a pivot-centric accelerator named PiHG to effectively support HGNN inference. Specifically, PiHG introduces a novel pivot-centric execution model into accelerator design to concentrate feature accesses and computations around pivot vertices, which enables reusing the feature vectors of overlapped vertices and edges across metapaths and thus eliminating redundant computations and reducing irregular off-chip memory accesses. Experimental results show that, compared with the state-of-the-art software and hardware solutions, PiHG achieves 13.1×∼236.8×, 2.2×∼11.7× speedups and 15.5×∼216.8×, 2.4×∼12.7× energy savings, respectively.

We propose TACo, a training-free, hardware-aware architecture search framework for Vision Transformers (ViTs), powered by a Hypervolume-based Unified Zero-Cost Score (HV-score) that integrates four accuracy- and hardware-related dimensions: a newly proposed zero-cost accuracy score (ZAS), latency, energy, and activation memory. TACo rapidly estimates the potential of candidate ViTs without training: ZAS captures layer-wise gradient stability, weight–gradient coupling, and gradient-modulated activation stability, while the HV-score guides multi-objective selection using Pareto and hypervolume principles. Experiments on CIFAR-10 and ImageNet-1K show that TACo reduces search time from GPU-days to GPU-hours while identifying a well-balanced ViT architecture in terms of accuracy and computational cost.

The prohibitively slow speed of long-context LLM decoding is a critical bottleneck, caused by massive Key-Value (KV) access that saturates memory bandwidth. Existing solutions fail due to a fundamental trade-off: static predictors cannot handle the Tokens Fluctuation, leading to permanent accuracy loss from irreversible eviction, while an on-the-fly scoring method creates a synchronous bottleneck that stalls the entire pipeline. This paper presents a co-designed system that breaks this trade-off by leveraging an Adaptive Prediction algorithm to enable a fully Decoupled Prefetching architecture. The proposed Adaptive Prediction model first mirrors the nature of Tokens Fluctuation, enabling a lightweight, reuse-based recovery mechanism that solves irreversible eviction. This high-fidelity prediction then unlocks the Decoupled Prefetching system, which completely hides data transfer latency and eliminates the synchronous bottleneck. On long-context LLM decoding tasks, the proposed system matches the accuracy of a full KV cache with just 256 tokens, while achieving an average 2.50x end-to-end speedup.

We present Janus, a compiler-based security framework that mit- igates transient execution attacks like Spectre and control-flow hijacking on ARM64 platforms. Janus integrates speculative execu- tion and control flow dependencies with PA modifiers, using PA and BTI microarchitectural features to prevent control-flow speculation attacks and secure both control flow and speculative execution through existing control-flow integrity mechanisms. To optimize performance, Janus minimizes overhead by merging defense opera- tions across different defense layers (modifier fusion) and reusing registers of protected variables (carrier reuse), while maintaining strong security guarantees. Evaluation on SPEC CPU2017 shows an average performance overhead of 3.85%, with real-world appli- cations exhibiting overheads ranging from 2.97% to 7.80%. Janus offers effective speculative execution security and low performance and code size overhead, making it a robust solution for ARM-based systems.

Sparse tensor operations underpin graph neural networks, scientific simulations, and data analytics, yet irregular sparsity leads to highly uneven tile densities and irregular memory access patterns, preventing GPUs from effectively utilizing Tensor Cores and CUDA cores. We present STCG, a compiler–runtime framework for sparse tensor code generation with adaptive tile scheduling on modern GPUs. STCG introduces a four-level IR that separates algebraic lowering, tiling, micro-kernel construction, and heterogeneous kernel assembly. The compiler emits a unified GPU kernel that embeds both WMMA-based Tensor Core micro-kernels and coordinate-indexed FMA kernels under a consistent memory and warp layout, ensuring stable register and shared-memory usage despite irregular sparsity. At runtime, lightweight tile descriptors enable constant-time, per-tile selection between the WMMA and FMA paths, providing data-aware load balancing and eliminating the need for kernel regeneration or manual tuning. On an NVIDIA A100, STCG achieves a 1.13$\times$ geometric-mean speedup over the per-dataset best existing method on SpMM and a 5.06$\times$ speedup on SpTTM, demonstrating the effectiveness and advancement of our approach across diverse sparsity patterns.

Near-DRAM Processing (NDP) has demonstrated great potential for memory-bound operators in edge-side large language model (LLM) inference. Featuring a xPU-NDP heterogeneous system, existing designs concentrate on optimizing the execution flow within processing units, yet ignoring the bottleneck arising from xPU-NDP data transfer. To tackle this challenge, we propose Maple, an efficient mapping exploration framework. Given a specific workload and NDP architecture, Maple adopts an address-mapping-based description method to construct a comprehensive search space that encompasses resource grouping, tensor partitioning and transfer binding, thereby facilitating joint optimization of computation and data transfer. Experiments show that Maple achieves an improvement of up to 3.34$\times$ in performance and 1.49$\times$ in energy compared with existing approaches on mainstream NDP architectures.

This paper presents Thrend, the first defense that mitigates counting threads used in timing side-channel attacks on Arm and Apple CPUs through real-time monitoring and scheduling. Thrend leverages fuzzing to automatically generate high-quality counting threads for training, and detects them by sampling hardware performance counters. For suspected counting threads, Thrend prevents effective timing measurements by co-scheduling the attacker threads and the counting threads on the same core. We implement Thrend on four ARM and Apple devices. Under the sampling rate of 100 Hz, Thrend achieves 99.71% detection accuracy, a 0% false-negative rate, and incurs less than 1.42% runtime overhead.

The deployment of large language models (LLMs) is increasingly targeting heterogeneous unified-memory architectures (HUMA) for edge and cost-sensitive computing. However, GPU-centric inference systems perform suboptimally on HUMA due to shared DRAM bandwidth contention and inefficient static operator placement. This paper introduces InferWeave, a bandwidth-aware inference framework that co-designs offline planning and runtime scheduling for HUMA. InferWeave's offline planner formulates operator placement and data staging as a unified optimization problem with DRAM bandwidth as a first-class constraint. At runtime, a bandwidth-aware asynchronous pipeline scheduler enforces these plans by regulating memory access rates, enabling non-blocking execution across host and device. Evaluated on LLaMA and GPT models using the MT-3000 processor, InferWeave achieves up to 2.3x higher throughput than FlexGen and llama2.c, demonstrating its effectiveness in enabling efficient LLM inference on integrated architectures.

Distributed training of Graph Neural Networks (GNNs) is hindered by communication overhead from exchanging embeddings and gradients. Existing quantization methods mitigate this cost by using shared bit widths at the layer or group level, followed by node-level uniform quantization, but such coarse granularity cannot fully exploit redundancy in long-tailed communication distributions. Entropy compression is well suited to these distributions, but static entropy compression schemes become less effective when training induces untracked distribution shifts. To address this issue, AdaHuff-GNN, a convergency-aware adaptive Huffman compression framework, is proposed to apply entropy compression to reduce communication cost in distributed GNN training. Within AdaHuff-GNN, loss-triggered codebook reconstruction and coarse-to-fine adaptive selection of codebook sizes jointly produce stage-wise codebooks that track distribution shifts. Binning-assisted clustering and conflict-free decoding reduce codec overhead on the communication critical path. Experiments show that AdaHuff-GNN reduces communication volume by 2.87× and shortens training epoch time by 37.5% over state-of-the-art methods without degrading model accuracy.

In modern high-density Printed Circuit Board (PCB) design, the conventional sequential workflow often leads to a fractured ground plane, compromising signal integrity and system performance. Existing Electronic Design Automation (EDA) tools passively fill unoccupied space with copper post-routing, lacking the ability to modify wire segments to improve ground plane continuity. In this paper, we propose A Ground Plane Generation and Re-routing Aware Co-design Engine, a novel, topology-aware framework that fundamentally shifts the paradigm from passive filling to an integrated co-design process. GRACE formulates ground plane generation as an optimization problem tightly coupled with automated rerouting. It partitions the layout into copper-pourable regions and blockages, and abstracts this into a novel weighted graph model, the Ground Plane Graph (GPGraph). We then formulate an Integer Linear Programming (ILP) problem on the GPGraph to identify a globally optimal set of blockages to eliminate. By strategically rerouting a minimal number of power & signal wire segments, GRACE merges isolated copper islands to create a maximum and contiguous ground plane. Experimental results demonstrate that GRACE drastically increases the area of the ground plane by an average of 33.06% and reduces the number of the ground plane polygons by 54.34% compared to open-source EDA tools. Moreover, our method achieves a significant speed-up over manual refinement while attaining an equivalent ground-plane area and number of ground plane polygons. To the best of our knowledge, this is the first work to automate ground plane unification through an integrated rerouting-aware co-design methodology.

RTL generators enable agile design of DNN accelerators, but the lack of early-stage power feedback forces designers to discover energy inefficiencies only after costly synthesis. Existing arch-level simulator-based approaches fall short for agile workflows: they require expertise and effort incompatible with rapid iteration. While machine learning struggles to capture software-hardware coupling, we reveal a key insight: compilation tells energy. Compiler toolchains in RTL generators already fuse workload and hardware characteristics—the coupling determining power. By extracting features from compiler IRs and multi-task learning, our methodology achieves practical accuracy through push-button workflows requiring no expertise. Validation on Gemmini and hls4ml demonstrates broad applicability, enabling true power-aware agile design.

Spiking neural networks (SNNs) represent a promising solution for emerging architectures due to high sparsity and low power consumption. Spiking Transformers extend these advantages to attention-based modeling and show strong potential for energy-efficient applications. However, their practical deployment remains difficult. Spiking transformers demand substantial computation and memory access because of long token sequences and heavy workloads in feed-forward networks. Moreover, existing sparse optimization methods provide limited benefit for spiking transformers since they either focus only on unstructured bit-level sparsity or require model retraining. This work presents ADAPT, an algorithm–hardware co-design that exploits the hierarchical sparsity of spiking transformers. At the algorithm level, we propose Adaptive Token Pruning (ATP), a training-free method that evaluates token diversity and spike activity to remove redundant tokens. At the hardware level, we design a hierarchical-sparse accelerator that introduces a block-sparsity compression format and a pattern processing unit to leverage repeated bit patterns inside non-zero blocks. Experiments on multiple spiking transformer models demonstrate that ATP prunes 50\% of tokens with negligible accuracy loss. The ADAPT accelerator achieves average speedups of 3.1x and 4.2x over state-of-the-art SNN accelerators Prosperity and GPU, while reducing energy by 1.9x and 149.4x. These results show that exploiting hierarchical sparsity with algorithm–hardware co-design enables efficient deployment of spiking transformers.

Trusted Execution Environments (TEEs) provide confidentiality and integrity, but their reliance on untrusted schedulers makes them vulnerable to CPU Denial-of-Service (DoS) attacks, compromising availability. Existing solutions either enlarge the Trusted Computing Base (TCB), rely on static closed-world workload assumptions that block dynamic enclave admission, or require hardware modifications. We propose AvaTEE, a lightweight framework for verifiable CPU availability in TEEs. AvaTEE uniquely integrates resource negotiation into remote attestation, providing a verifiable resource commitment pre-deployment. At runtime, a trusted scheduler performs dynamic monitoring and preemptive arbitration to mitigate DoS attacks. We evaluate AvaTEE on an FPGA. The results demonstrate that it (1) provides robust protection under contention, where native TEEs suffer a 94.8\% performance loss and up to a 19.7$\times$ slowdown; (2) incurs negligible overhead (less than 2\%) during enclave startup and normal runtime; and (3) maintains near-native performance, with only 1.70\% average overhead compared to Keystone.

Previous studies have verified that some special Performance Monitoring Unit (PMU) events are insecure. In this work, we further disclose that even the PMU events are securely designed and implemented, they are capable of constructing malicious attacks. We develop and implement a fuzz testing framework to automatically identify and verify numerous PMU events. Based on which, we successfully discover 118 vulnerable PMU events. Leveraging these identified events, we introduce PMU-Faker, a precise timing mechanism that can implement most of the timing-based side channel attacks without timer. To accommodate variations in instruction-triggered cycle durations, PMU-Faker provides two timing mechanisms with varying levels of granularity, thereby balancing precision and adaptability. Moreover, we successfully utilizing PMU-Faker to implement four attacks including executing transient execution attacks, extracting AES's key, conducting attacks against Intel Software Guard Extensions (SGX), and achieving cross-virtual machine information leakage.

The interrupt is a significant mechanism for computer systems to schedule hardware resources. We find that some hardware interrupts are not well-managed so that they can expose low-level events to unprivileged software, which introduce unanticipated security risks. We first design an automated testing framework to identify the interrupts' working features and trigger condition, which helps us discover six vulnerable interrupts. Next, we design a novel set of attack primitives for leaking secrets using them. Finally, we realize four attacks with the proposed attack primitives: leaking contents from a restricted directory, fingerprinting DNN model architectures, classifying processes, and enhancing Spectre attacks.

Three-dimensional (3D) point cloud models have been widely employed in modern 3D perception tasks such as robotics, autonomous driving, and virtual reality. The k-nearest-neighbor (KNN) search serves as a cornerstone operation for point cloud models, providing the essential mechanism for defining and exploiting local spatial relationships within unstructured data. However, the massive scale of point cloud data and the high computational complexity of Euclidean distance-based top-k searches in KNN impose substantial computational overhead. Conventional edge computing platforms struggle to achieve real-time and high efficiency of point cloud processing. In this work, we propose KCD-CAM, a KNN accelerator using ReRAM-based charge-domain content-addressable memory (CAM) for efficient point cloud processing. The proposed KCD-CAM employs a 4T2R CAM cell capable of performing in-situ range search, effectively replacing complex Euclidean distance calculations with massively parallel operations. In addition, corner-clipped (CC) iterative top-k search scheme and dual-granularity voxel hashing (DG-VH) are employed to enhance accuracy and parallelism. Performance benchmarks in real-world datasets demonstrate that KCD-CAM achieves 279.79× higher speed and 3282× greater energy efficiency than GPU implementations. Compared to the SOTA KNN accelerators, our KCD-CAM also achieved 8.51× and 4.76× improvements in speed and energy efficiency, respectively.

Chiplet accelerators offer a scalable solution for LLM inference with reduced manufacturing costs. However, the design space exploration (DSE) of chiplet accelerators is challenging due to the complex design space. Prior black-box Bayesian optimization (BO) solutions lack domain knowledge, limiting their effectiveness. In this work, we propose AgenticDSE, a multi-agent DSE framework that incorporates the collaboration of three LLM agents, i.e., exploration orchestrator, architecture analyst, and optimization engineer. This multi-agent framework enhances exploration efficiency through analysis-driven design space refinement and phase-wise design exploration using ensemble surrogate modeling. Over the same number of explorations, AgenticDSE achieves up to 36.9% reduction of average distance to the real Pareto front, and 66% increase in diversity of explored Pareto front compared to state-of-the-art DSE solutions. Additionally, it offers scalable performance with 46x and 18x reduction in input and output token consumption compared to prior LLM-based solutions.

With the rapid advancement of Artificial Intelligence, the Graphics Processing Unit (GPU) has become increasingly essential across a growing number of safety-critical application domains. Applying a GPU is indispensable for parallel computing; however, the complex data dependencies and resource contention across kernels within a GPU task may unpredictably delay its execution time. To address these problems, this paper presents a scheduling and analysis method for Directed Acyclic Graph (DAG)-structured GPU tasks. Given a DAG representation, the proposed scheduling scales the kernel-level parallelism and establishes inter-kernel dependencies to provide a reduced and predictable DAG response time. The corresponding timing analysis yields a safe yet non-pessimistic makespan bound without any assumption on kernel priorities. The proposed method is implemented using the standard CUDA API, requiring no additional software or hardware support. Experimental results under synthetic and real-world benchmarks demonstrate that the proposed approach effectively reduces the worst-case makespan and measured task execution time compared to the existing methods up to $32.8\%$ and $21.3\%$, respectively.

Detailed routing, despite its long history of study, is considered one of the most challenging problems in Electronic Design Automation, due to complex design rules and enormous scale. In this work, we propose a versatile maze routing algorithm to deal with the various challenges in detailed routing. By introducing hybrid grid graph, our maze routing algorithm can create both on-track and off-track wires during path search. By adopting a scalable track-based resource model and techniques like adaptive grid graph sparsification, it can handle both large guide-based and small region-based grid graphs. Moreover, we also propose a simple and effective rip-up and reroute strategy. As a result, we achieve design rule violation-free on most designs (9/10) in the ISPD 2018 detailed routing benchmarks, with 2.5% better score, 4.6% fewer vias, and 14.7% shorter runtime on average, and significantly lower non-preferred usage, compared with the state-of-the-art approaches.

The increasing adoption of GPUs in real-time systems necessitates precise timing analysis for GPU thread blocks to ensure overall system predictability. However, the uncertainties of branch executions within GPU warps impose significant barriers for predicting the worst-case execution time (WCET) of the thread block. Existing WCET analysis for thread blocks typically assumes deterministic warp execution paths, which is unrealistic given the dynamic control flows of threads within the warps. Moreover, as the warp scheduler operates as a black box, the analysis must rely on relaxed scheduling assumptions, resulting in overly-pessimistic bounds in order to cover edge scenarios. This paper first establishes the need for static analysis by showing how branch divergence can trigger timing anomalies and influence block WCETs. We then develop an exact WCET analysis for a GPU thread block under the same scheduling constraints as prior work while not imposing any warp execution path assumptions. Furthermore, by enforcing a practical constraint on warp executions, we present a tighter analysis that enhances system predictability. Experiments show that the proposed analysis under warp execution constraints significantly reduces the WCET estimations of GPU thread blocks (by 19.13% on average and up to 39.39%).

Graph-based Approximate Nearest Neighbor Search (GANNS) has been widely adopted for vector retrieval owing to its high scalability and low latency. However, existing GANNS frameworks face severe latency bottlenecks on billion-scale datasets due to excessive SSD I/O. This work presents LOHA, a latency-optimized CPU–storage hybrid architecture for product quantization (PQ)-based billion-scale ANNS. LOHA decouples graph traversal and re-ranking workloads, executing the former on the CPU while offloading the latter to an in-storage accelerator that exploits SSD-level parallelism. Furthermore, a speculative re-ranking mechanism pipelines both stages to minimize idle time and reduce end-to-end latency. Experiments show that LOHA achieves throughput improvements of up to 9.6x, 6.2x, and 4.0x over CPU-, GPU-, and in-storage architectures, respectively.

Standard cell library characterization is a critical bottleneck for timing closure. Existing machine learning (ML) surrogates reduce SPICE costs but are constrained by labeled data requirements, limiting accuracy. This work introduces PG-GNN, a Physics-Guided Graph Neural Network (GNN) framework integrating residual learning with uncertainty-driven active learning. It simulates sparse anchor PVT corners, builds a physics-consistent reference, and trains a GNN on residual errors. Active learning then queries high-uncertainty points to minimize labeling. In experiments on TSMC 16 nm libraries, PG-GNN reduces SPICE effort by 98.7% with 1.67% MAPE. When applied to ISCAS'89 benchmarks, it achieves 0.74% critical path delay mismatch versus foundry libraries. PG-GNN offers orders-of-magnitude speedups in characterization runtime while maintaining signoff-level accuracy, presenting a scalable solution for next-generation IC design flows.

With the development of deep neural network (DNN) enabled applications, achieving high hardware resource efficiency on diverse workloads is non-trivial in heterogeneous computing platforms. Prior works discuss dedicated architectures to achieve maximal resource efficiency. However, a mismatch between hardware and workloads always exists in various diverse workloads. Other works discuss overlay architecture that can dynamically switch dataflow for different workloads. However, these works are still limited by flexibility granularity and induce much resource inefficiency. To solve this problem, we propose a flexible composing architecture, FILCO, that can efficiently match diverse workloads to achieve the optimal storage and computation resource efficiency. FILCO can be reconfigured in real-time and flexibly composed into a unified or multiple independent accelerators. We also propose the FILCO framework, including an analytical model with a two-stage DSE that can achieve the optimal design point. We also evaluate the FILCO framework on the 7nm AMD Versal VCK190 board. Compared with prior works, our design can achieve 1.3x - 5x throughput and hardware efficiency on various diverse workloads.

The rapid growth of LLMs demands high-throughput, memory-capacity–intensive inference on resource-constrained edge devices, where single-batch decoding remains fundamentally memory-bound. Existing out-of-core GPUs and SSD-like accelerators are limited by DRAM-bound weight movement and inefficient storage-access granularity. We present NVLLM, a 3D NAND-centric inference architecture that offloads FFN computation into the Flash array while executing attention on lightweight CMOS logic with external DRAM. Through wafer-to-wafer stacking, NVLLM tightly integrates multi-plane 3D NAND with compute pipelines, ECC units, and buffers, enabling page-level FFN weight access without DRAM traversal. All GEMM/GEMV operations are decomposed into dot-product primitives executed by out-of-order PE lanes, operating directly on raw NAND reads with integrated ECC. Attention weights remain in DRAM, and a KV-cache–aware scheduler maintains throughput as context grows. Evaluated on OPT and LLaMA models up to 30B parameters, NVLLM achieves 16.7× speedup over A800 out-of-core inference and 1.1×–4.7× improvement over SSD-like designs, with only 2.7\% CMOS area overhead.

MoE models offer efficient scaling through conditional computation, but their large parameter size and expensive expert offloading make on-device deployment challenging. Existing acceleration techniques such as prefetching or expert clustering often increase energy usage or reduce expert diversity. We present SliceMoE, an energy-efficient MoE inference framework for miss-rate–constrained deployment. SliceMoE introduces Dynamic Bit-Sliced Caching (DBSC), which caches experts at slice-level granularity and assigns precision on demand to expand effective expert capacity. To support mixed-precision experts without memory duplication, we propose Calibration-Free Asymmetric Matryoshka Quantization (AMAT), a truncation-based scheme that maintains compatibility between low-bit and high-bit slices. We further introduce Predictive Cache Warmup (PCW) to reduce early-decode cold misses by reshaping cache contents during prefill. Evaluated on DeepSeek-V2-Lite and Qwen1.5-MoE-A2.7B, SliceMoE reduces decode-stage energy consumption by up to 2.37× and 2.85×, respectively, and improves decode latency by up to 1.81× and 1.64×, while preserving near–high-bit accuracy. These results demonstrate that slice-level caching enables an efficient on-device MoE deployment.

Autonomous driving systems increasingly rely on deep neural network (DNN) based multi-task perception models for reliable, real time scene understanding. At nanoscale technology nodes, these workloads are highly susceptible to timing errors arising from temperature fluctuations, voltage droop, and device aging. Among these, temperature poses a critical challenge prolonged high thermal stress exacerbates delay faults, degrading perception accuracy and endangering safety-critical operation. We present DFA DRIVE, a cross-layer Delay Fault Analysis Framework for Autonomous Driving that bridges circuit-level timing analysis with system level resilience evaluation. DFA DRIVE quantifies how temperature induced timing failures propagate through object detection, drivable area segmentation, and lane line segmentation, exposing task level reliability bottlenecks. Building on this foundation, we introduce DFA-OPT, an adaptive DNN hardware mapping algorithm that dynamically reassigns systolic-array resources based on DNN layer and applicaiton level thermal sensitivity. Targeting the automotive reliability envelopes of AEC-Q100 Grade 0 (–40 °C to 150 °C) and Grade 1 (–40 °C to 125 °C), DFA-OPT restores near baseline accuracy of small, high reliability systolic arrays (e.g., 4×4) even when large systolic arrays (e.g., 256×256) experience accuracy drops of up to 4% at 150 °C, achieving comparable accuracy with up to 92% fewer computation cycles.

Accurate frequency measurement in high-speed data streams is crucial. While FPGA-based solutions are promising, existing designs often trade off throughput against accuracy due to limited hardware resources. This paper introduces CelestialEye, a CPU-FPGA synergistic architecture that employs a CPU-based heuristic decoding algorithm for high accuracy and offloads high-throughput tasks to the FPGA. Its pipelined hardware integrates hot/cold item separation, advanced compression, and encoding to optimize on-chip SRAM efficiency and bandwidth utilization. Furthermore, the frequency bounds generated by the FPGA process can accelerate the CPU's decoding. Experimental results demonstrate that CelestialEye significantly outperforms the state-of-the-art BitMatcher in both performance and accuracy.

Graph-based retrieval-augmented generation (RAG) improves the interpretability and factual consistency of large language models (LLMs) through structured knowledge graphs. Despite these benefits, graph-based RAG suffers from inefficient retrieval. The retrieval stage causes massive movement of vector and graph data between memory and processors. This movement leads to low arithmetic intensity and heavy pressure on memory bandwidth. This work presents PIMGRAG, a heterogeneous architecture that accelerates graph-based RAG through hardware/software co-design. At the hardware level, PIMGRAG designs a PIM architecture for the retrieval stage, which reduces off-chip data transfer by executing bandwidth-intensive operations near memory. At the software level, PIMGRAG applies a lightweight scheduling method that orchestrates PIM and GPU execution and lowers idle time across stages. Evaluation results show improvements in throughput, latency, and energy efficiency over CPU–GPU and existing PIM-based baselines.

Trillion-parameter Transformers across vision, language, and action increasingly rely on reduced - precision floating- point (e.g., FP8) for dynamic range and efficiency. While their compute-intensive operations might make in-memory solutions attractive, the incompatibility of FP operations with analog computing renders many optimizations untenable for emerging compute-in/near-memory (CIM/CNM) platforms. To address this incompatibility, we present MANTIS, a foundry- SRAM -compatible, mixed-signal, CNM/CIM macro that performs vector integer multiply-accumulate opera- tions in the analog charge domain, while applying per-vector FP8 scaling factors digitally via microscaling (MXFP). The proposed design, in a commercially available 12 nm node, reuses the digital-to-analog converter (DAC) in a successive approximation register (SAR) analog-to-digital converter (ADC) as both a bit-plane charge-domain accumulator and as part of the ADC. The design is implemented as a 4kb macro, operating at 0.8V. Our 8b ADC delivers 7.62 effective number of bits (ENOB), resulting in a precision-scalable efficiency of 22.5 TOPS/W (for MXINT3×MXINT3) to 6.43 TOPS/W(MXINT8×MXINT3). In end-to-end evaluations on MMLU (5-shot) and HellaSwag (0-shot), our design only incurs a 0.15 percentage point accuracy degradation across multiple open-weight LLMs (vs. the MXINT8 activation × MXINT3 weight, quantized baseline). For reduced-precision activations (MXINT6 / MXINT3 + FP8 scalar), our results track within ±0.3% of the quantized models, with minimal impact from analog computation.

We present a directional-transport (DT)-based remote CZ gate and compiler for zoned neutral-atom arrays that overcomes movement-bound entanglement limitations. Current AOD-based shuttling faces row/column non-crossing constraints, device-speed limits, and FOV/NA-restricted range—bottlenecks for long-distance connectivity. Our approach reserves AODs for channel setup and micro-tuning while making DT the default for remote entanglement. Under antiblockade, a detuning-modulated pi-pulse sequence drives directional transport of a Rydberg excitation along a dynamic and resettable ancilla corridor, realizing a CZ gate between stationary, non-adjacent qubits. This cuts entangling-stage duration by approximately 50% -90% versus AOD-only baselines and enables long-distance connectivity beyond objective-limited shuttling.

Complex-Valued Neural Networks (CVNNs) have significant advantages in handling tasks that involve complex numbers. However, existing CVNNs are unable to quantify predictive uncertainty. We propose, for the first time, dropout-based Bayesian Complex-Valued Neural Networks (BayesCVNNs) to enable uncertainty quantification for complex-valued applications, exhibiting broad applicability and efficiency for hardware implementation due to modularity. Furthermore, as the dual-part nature of complex values significantly broadens the design space and enables novel configurations based on layer-mixing and part-mixing, we introduce an automated search approach to effectively identify optimal configurations for both real and imaginary components. To facilitate deployment, we present a framework that generates customized FPGA-based accelerators for BayesCVNNs, leveraging a set of optimized building blocks. Experiments demonstrate the best configuration can be effectively found via the automated search, attaining higher performance with lower hardware costs compared with manually crafted models. The optimized accelerators achieve approximately 4.5× and 13× speedups on different models with less than 10% power consumption compared to GPU implementations, and outperform existing work in both algorithm and hardware aspects. The code will be open-source after acceptance.

Recent advances in large language models (LLMs) have demonstrated significant potential in hardware design automation, particularly in using natural language to synthesize Register-Transfer Level (RTL) code. Despite this progress, a gap remains between model capability and the demands of real-world RTL design, including syntax errors, functional hallucinations, and weak alignment to designer intent. Reinforcement Learning with Verifiable Rewards (RLVR) offers a promising approach to bridge this gap, as hardware provides executable and formally checkable signals that can be used to further align model outputs with design intent. However, in long, structured RTL code sequences, not all tokens contribute equally to functional correctness, and naïvely spreading gradients across all tokens dilutes learning signals. A key insight from our entropy analysis in RTL generation is that only a small fraction of tokens (e.g., always, if, assign, posedge) exhibit high uncertainty and largely influence control flow and module structure. To address these challenges, we present EARL, an Entropy-Aware Reinforcement Learning framework for Verilog generation. EARL performs policy optimization using verifiable reward signals and introduces entropy-guided selective updates that gate policy gradients to high-entropy tokens. This approach preserves training stability and concentrates gradient updates on functionally important regions of code. Our experiments on VerilogEval and RTLLM show that EARL improves functional pass rates over prior LLM baselines by up to 14.7%, while reducing unnecessary updates and improving training stability. These results indicate that focusing RL on critical, high-uncertainty tokens enables more reliable and targeted policy improvement for structured RTL code generation. We will release the code upon acceptance. An anonymized repository for review is available at https://anonymous.4open.science/r/EARL-1C25.

Adversarial patches are physically realizable localized noise, which are able to hijack Vision Transformers (ViT) self-attention, pulling focus toward a small, high-contrast region and corrupting the class token to force confident misclassifications. In this paper, we claim that the tokens which correspond to the areas of the image that contain the adversarial noise, have different statistical properties when compared to the tokens which do not overlap with the adversarial perturbations. We use this insight to propose a mechanism, called STRAP-ViT, which uses Jensen-Shannon Divergence as a metric for segregating tokens that behave as anomalies in the Detection Phase, and then apply randomized composite transformations on them during the Mitigation Phase to make the adversarial noise ineffective. The minimum number of tokens to transform is a hyper-parameter for the defense mechanism and is chosen such that at least $50\%$ of the patch is covered by the transformed tokens. STRAP-ViT fits as a non-trainable plug-and-play block within the ViT architectures, for inference purposes only, with a minimal computational cost and does not require any additional training cost/effort. STRAP-ViT has been tested on multiple pre-trained vision transformer architectures (ViT-base-16 and DinoV2) and datasets (ImageNet and CalTech-101), across multiple adversarial attacks (Adversarial Patch, LAVAN, GDPA and RP2 ), and found to provide robust accuracies lying within a 2-3% range of the clean baselines, and outperform the state-of-the-art.

Hyperdimensional Computing (HDC) encodes information and data into high-dimensional distributed vectors that can be manipulated using simple bitwise operations and similarity searches, offering parallelism, low-precision hardware friendliness, and strong robustness to noise. These properties are a natural fit for SQL database workloads dominated by predicate evaluation and scans, which demand low energy and low latency over large fact tables. Notably, HDC's noise-tolerance maps well onto emerging ferroelectric NAND (FeNAND) memories, which provide ultra-high density and in-storage compute capability but suffer from elevated raw bit-error rates. In this work, we propose HDDB, a hardware–software co-design that combines HDC with FeNAND multi-level cells (MLC) to perform in-storage SQL predicate evaluation and analytics with massive parallelism and minimal data movement. Particularly, we introduce novel HDC encoding techniques for standard SQL data tables and formulate predicate-based filtering and aggregation as highly efficient HDC operations that can happen in-storage. By exploiting the intrinsic redundancy of HDC, HDDB maintains correct predicate and decode outcomes under substantial device noise (up to 10% randomly corrupted TLC cells) without explicit error-correction overheads. Experiments on TPC-DS fact tables show that HDDB achieves up to 80.6× lower latency and 12,636× lower energy consumption compared to conventional CPU/GPU SQL database engines, suggesting that HDDB provides a practical substrate for noise-robust, memory-centric database processing.

Accurate and efficient lithography simulation is critical for virtual fabrication and shift-left manufacturing. While thin-mask models and single-plane aerial images suffice at older nodes, advanced nodes require 3D in-resist aerial images to capture depth-dependent effects from mask thickness, sidewalls, and multilayer stacks. Rigorous EM solvers provide this fidelity but are too slow for ILT or full-chip use, and thin-mask learning methods fail to model the underlying vector field needed for 3D propagation. This paper introduces a new paradigm that reconstructs the full 3D in-resist vector field from the image-plane vector field and 3D mask/film-stack parameters. Based on this insight, we develop N3Litho, a GPU-native numerical-neural framework that couples a GPU-accelerated vectorial Abbe solver with an NGP-based multi-resolution hash backbone for fast 3D field reconstruction. The method achieves near-EM fidelity with orders-of-magnitude speedup, and the resulting 3D aerial images can be directly used by resist models, OPC/ILT pipelines, and hotspot detection flows

Hardware security competitions such as HackTheSilicon serve as benchmarking platforms for evaluating vulnerability detection methods and training human and AI. However, our study reveals that LLMs threaten their validity. Instead of genuine security reasoning, detectors exploit a diff-style syntactic comparison, achieving an 83% detection rate, undermining fair evaluation. To mitigate this, we propose the first LLM-oriented, semantics-preserving obfuscation framework for these benchmarks. Unlike IP-protection approaches, it applies human-readable transformations and controlled diff-noise while preserving functionality. On HackTheSilicon, the framework reduces LLM-based detection accuracy by 50% with only 10% obfuscation and by 78.6% under complete obfuscation, restoring benchmark reliability.

Approximate Nearest Neighbor (ANN) search has become fundamental to modern AI infrastructure, powering recommendation systems, search engines, and large language models across industry leaders from Google to OpenAI. Hierarchical Navigable Small World (HNSW) graphs have emerged as the dominant ANN algorithm, widely adopted in production systems due to their superior recall vs. latency balance. However, as vector databases scale to billions of embeddings, HNSW faces critical bottlenecks: memory consumption expands, distance computation overhead dominates query latency, and it suffers suboptimal performance on heterogeneous data distributions. This paper presents Adaptive Quantization and Rerank HNSW (AQR-HNSW), a novel framework that synergistically integrates three strategies to enhance HNSW's scalability. AQR-HNSW introduces (1) density-aware adaptive quantization, achieving 4× compression while preserving distance relationships; (2) multi-state re-ranking that reduces unnecessary computations by 35%; and (4) quantization-optimized SIMD implementations delivering 16-64 operations per cycle across architectures. Evaluation on standard benchmarks demonstrates 2.5-3.3× higher QPS than state-of-the-art HNSW implementations while maintaining 98%+ recall, with 75% memory reduction for the index graph and 5× faster index construction.

Prefix KV cache is widely used to accelerate LLM serving by trading more storage for less computation, and state-of-the-art methods often replicate hotspot caches for load balancing. However, we observe that the few nodes that have cache replicas still lead to severe load imbalance. This paper presents ECPrefix: a new prefix KV cache framework based on erasure coding (instead of replication), which distributes encoded blocks of hot prefix caches (organized as profile-guided objects) across nodes, along with adaptive striping and pipelined reading optimizations. Evaluation shows that ECPrefix reduces TTFT by up to 52.3% over existing systems.

In the integrated circuit design flow, a high-level specification is synthesized into a gate-level netlist. However, this synthesis often results in the loss of the association between the high-level and gate-level designs. Maintaining signal correspondences between these two levels is crucial for preserving the design hierarchy, which in turn facilitates design debugging, engineering change orders (ECOs), cross-abstraction-level model training, and other synthesis and verification tasks. In this work, we present an automated approach for recovering the hierarchical boundaries of high-level components in gate-level netlists, even in cases where the synthesis process has completely removed the original boundary signals. The method is implemented as an open-source tool, and the experimental results demonstrate its robustness in recovering hierarchical boundaries. Our results may benefit various potential applications in synthesis and verification.

Many-core neuromorphic systems serve as specialized accelerators for Spiking Neural Networks (SNNs). However, the communication mechanisms in existing neuromorphic systems incur significant traffic and energy overhead due to redundant address transmissions, a bottleneck exacerbated by the short payloads inherent to the spike-based communication nature of SNNs. Specifically, our characterization reveals that in current neuromorphic systems, duplicate address transmissions can account for up to 49% of the total traffic in representative workloads. This paper presents UniSpike, a hardware-software co-design that eliminates address redundancy by aggregating spikes destined for the same core into single, compact packets. UniSpike implements a spike transmission scheduling strategy to enable efficient spike merging, supported by a dedicated hardware architecture for runtime packet assembly and dispatch, as well as a destination-aware SNN partitioning algorithm that maximizes address sharing opportunities. Experimental results demonstrate that on average, UniSpike reduces traffic volume by 1.93x, achieving 1.77x speedup and 1.50x energy efficiency improvement over state-of-the-art designs.

Yield Multi-Corner Analysis validates circuits across 125+ Process-Voltage-Temperature corners, creating combinatorial simulation cost of $O(K \times N)$ where $K$ denotes corners and $N$ exceeds $10^5$ samples per corner. Existing methods face a fundamental trade-off: simple models achieve automation but fail on nonlinear circuits, while advanced AI models capture complex behaviors but require hours of hyperparameter tuning per design iteration, forming the Tuning Barrier. We break this barrier by replacing engineered priors (i.e., model specifications) with learned priors from a foundation model pre-trained on millions of regression tasks. This model performs in-context learning, instantly adapting to each circuit without tuning or retraining. Its attention mechanism automatically transfers knowledge across corners by identifying shared circuit physics between operating conditions. Combined with an automated feature selector (1152D to 48D), our method matches state-of-the-art accuracy (mean MREs as low as 0.11\%) with zero tuning, reducing total validation cost by over $10\times$.

Probabilistic computation plays an important role in trustworthy edge intelligence to quantify uncertainty, enhance robustness, reconstruct data and protect privacy, but its adoption is limited by orders of magnitude data throughput gap between Gaussian random number generation(GRNG) and computation, as well as instruction overhead. This paper introduces \emph{probabilistic memory} (p-MEM), a unified memory primitive that stores distribution parameters and samples directly at native memory bandwidth where deterministic data becomes the zero-variance special case. Using a layout-validated p-MEM simulator, we comprehensively explore device choices, memory specifications, and technology nodes, showing that p-MEM can achieve $>1000$\,GSa/s/mm$^2$ GRNG throughput (including memory arrays). Integrated into CPU / GPU systems, p-MEM reduces instruction count by up to $2.19\times$/$4.37\times$, sampling latency by $562\times$/$3.45\times$, and energy by $295.5\times$/$3.53\times$ for BNN workloads, providing a scalable hardware substrate for trustworthy probabilistic AI.

Microcontroller Units (MCUs) are widely used in safety-critical systems, making them frequent attack targets. This demands lightweight defenses that remain reliable even after software compromise. Control Flow Auditing (CF-Aud) strengthens Control Flow Attestation by ensuring authenticated control-flow logs (CFLogs) are reliably delivered from a compromised prover (Prv) to a remote verifier (Vrf), enabling assessment of system behavior and support for remediation. However, existing CF-Aud designs rely on a costly busy-wait phase that limits Prv's utilization. In this work, we propose CARAMEL: a hybrid hardware-software root-of-trust architecture that reduces this bottleneck by enabling log transmission without halting execution. Its minimal communication interface and implementation are open-source.

Always-on vision is essential for smart glasses, yet continuous visual-processing under stringent power budgets remains a major challenge. This work presents an always-on visual wakeup acceleration-engine for sub-milliwatt hand gesture recognition. A compact convolutional neural network (<13k parameters), trained on the HaGRID dataset, performs binary classification on 64×64 inputs achieving over 92% accuracy at 3b precision, requiring less than 9kB of memory. When executed on a flexible accelerator engine implemented in 7nm technology, at 100MHz, it consumes only 64nJ per frame, translating to always-on power of 11μW at 30FPS, enabling energy-efficient, always-on interaction for next-generation smart-glasses.

Recent advances in large language models (LLMs) have driven exponential growth in parameter counts, amplifying memory footprints and creating acute computational bottlenecks. Weight-only quantization is a common mitigation because weights dominate storage and incur less accuracy degradation than activation quantization. However, it leaves activations in floating point (FP), forcing FP execution whose area and energy costs far exceed those of integer (INT) compute. To address this limitation, binary coding quantization (BCQ) lowers this cost by replacing many FP multiplies with FP additions, but still requires FP multiplications for scaling factors and suffers from limited representational capacity, causing non-trivial accuracy loss. In this paper, we propose a sum-of-power-of-two scaling factor–based BCQ (SS-BCQ) that approximates FP scaling factors with a small set of power-of-two terms, eliminating FP multiplications (shift–add only) while preserving accuracy. To efficiently realize SS-BCQ in hardware, we introduce CORE, a fully pipelined FP–INT general matrix-matrix multiplication (GEMM) engine. CORE features (i) an adaptive data-mapping module that computes optimized block-wise activation scales to minimize scaling operations, and (ii) an extra processing unit that allocates a small subset of processing elements to high-importance weights to retain accuracy at low cost. Evaluated on the OPT-6.7B model, SS-BCQ reduces perplexity by 3.14 compared with prior BCQ methods. Implemented in CORE, our approach achieves up to 1.41x higher area efficiency (TOPS/mm^2) and 2.18x higher energy efficiency (TOPS/W) than state-of-the-art FP–INT accelerators, enabling a homogeneous low-precision execution path for on-device LLMs.

Recent experimental progress in surface-code hardware, including demonstrations of break-even logical memory on devices with up to hundreds of physical qubits, has materially advanced the prospects for fault-tolerant quantum computation. This progress creates ur- gency for compilation workflows that directly target the forth- coming generation of devices with thousands of physical qubits, for which algorithm execution becomes practical. We develop a pipeline for compiling logical algorithms to physical circuits imple- menting lattice surgery on the surface code, and use this pipeline to identify the requirements for achieving algorithmic break-even— where quantum error correction improves the performance of a quantum algorithm—for the quantum approximate optimization algorithm (QAOA). Our pipeline integrates several open-source software tools, and leverages recent advances in error-aware uni- tary gate synthesis, high-fidelity magic-state production, and the calculation of correlation surfaces in the surface code. We apply our pipeline by performing classical simulations of physical Clifford proxy circuits produced by our pipeline, and find that 5-qubit QAOA can reach algorithmic break-even with 2517 physical qubits (surface code distance 𝑑 = 11) at physical error rates of 𝑝 = 10−3, or 1737 physical qubits (𝑑 = 9) at 𝑝 = 5 × 10−4. Our work thereby identifies conditions for achieving algorithmic break-even with near-term quantum hardware and paves the way towards an end-to-end com- piler for early-fault-tolerant surface code architectures

Coarse-grained reconfigurable arrays (CGRAs) are programmable hardware devices having large coarse-grained processing elements (PEs) and word-wide configurable interconnect. The interconnect comprises a considerable fraction of total CGRA area, making it desirable to restrict interconnect connectivity richness. However, reducing interconnect richness makes application mapping more difficult, and impossible in some cases. We propose techniques for mapping applications onto CGRAs with restricted routing architectures. For a target CGRA having restricted interconnect, we precompute the reachability and distance between all PE pairs, as well as an estimate of the number of available routing paths between PE pairs. The values are stored in tables, and used during the placement stage of the mapping flow to assess the potential routability of an intermediate placement. For benchmark applications mapped onto CGRA variants with restricted interconnect, results demonstrate higher mapping success, and lower mapping runtimes vs. recent state-of-the-art CGRA mappers.

Microcontrollers lack support for virtual addressing, limiting their ability to employ efficient memory protection mechanisms that rely on a spacious virtual address space. While integrating an MMU could overcome this limitation, it is often impractical due to increased hardware cost and unpredictable latency. To address this, we propose \textit{semi-virtual addressing}—a lightweight technique that extends the effective address space of microcontrollers without full virtual memory support. This technique introduces a Lightweight Address Translation Module (LATM) that performs deterministic, computation-based address translation without page tables, enabling semi-virtual addressing with minimal translation overhead. Implemented on the RISC-V CORE-V-MCU, LATM expands its 575 KB physical address space to 2 GB of semi-virtual address space. We demonstrate the practicality of semi-virtual addressing by enabling heap randomization and type-safe allocation on the extended address space, efficiently enhancing memory protection.

Quantum computing imposes stringent requirements for the precise control of large-scale qubit systems, including, for example, microsecond-latency feedback and nanosecond-precision timing of gigahertz signals – demands that far exceed the capabilities of conventional real-time systems. The rapidly evolving and highly diverse nature of quantum control necessitates the development of specialized hardware accelerators. While a few custom real-time systems have been developed to meet the tight timing constraints of specific quantum platforms, they face major challenges in scaling and adapting to increasingly complex control demands – largely due to fragmented toolchains and limited support for design automation. To address these limitations, we present RISC-Q – an open-source flexible generator for Quantum Control System-on-Chip (QCSoC) designs, featuring a programming interface compatible with the RISC-V ecosystem. Developed using SpinalHDL, RISC-Q enables efficient automation of highly parameterized and modular QCSoC architectures, supporting agile and iterative development to meet the evolving demands of quantum control. We demonstrate that RISC-Q can surpass the performance of existing QCSoCs with significantly reduced development effort, facilitating efficient exploration of the hardware-software co-design space for rapid prototyping and customization.

Masking is an effective defense against side-channel attacks, yet it remains costly under hardware constraints. The Caliptra Root-of-Trust is a representative case, where its masked ML-DSA implementation incurs about 6× area overhead. We propose a novel first-order masking solution that optimizes Caliptra, achieving significant improvements in area–delay efficiency. Compared to Caliptra's ML-DSA reduction, our design achieves a 12.1× speedup, reducing LUTs by 86.7% and FFs by 94.5%, while improving area–delay efficiency by 91×. The optimized architecture increases signing throughput by 1.32×. TVLA, with over 1,000,000 traces, shows no first-order leakage, satisfies Caliptra's security requirements, and significantly improves implementation efficiency.

Scientific machine learning (SciML) field deployment faces communication bottlenecks from centralized architectures, while distributed approaches violate physical principles. We introduce EPIC, a hardware-physics co-guided framework using full-waveform inversion as a representative task. EPIC performs lightweight edge encoding and physics-aware central decoding, transmitting compact latents instead of raw data. Cross-attention preserves inter-receiver wavefield coupling while reducing communication costs. Evaluated on five Raspberry Pi devices across 10 OpenFWI datasets, EPIC reduces latency by 8.9× and communication energy by 33.8×, while improving reconstruction fidelity on 8 out of 10 datasets compared to centralized approaches.

Automatic generation of RTL code for digital hardware designs remains challenging due to long-horizon reasoning, multi-step dependencies, and strict correctness constraints in Verilog and VHDL. We present StepPRM-RTL, a novel framework that combines stepwise trajectory modeling, process-reward modeling (PRM), and retrieval-augmented fine-tuning (RAFT) to enhance both the functional correctness and reasoning fidelity of LLM-based RTL code generation. StepPRM-RTL constructs stepwise reasoning trajectories from canonical solutions, where each step contains a rationale and incremental code modification. A Process Reward Model (PRM) evaluates intermediate steps, providing dense feedback that guides reinforcement-style updates during RAFT fine-tuning. Monte Carlo Tree Search (MCTS) explores alternative reasoning paths, enriching the training dataset with high-quality trajectories. This integration of stepwise and outcome-aware rewards allows the model to learn both how and why to construct correct RTL, improving long-horizon reasoning beyond standard supervised or outcome-based training. Experimental evaluation on benchmark Verilog and VHDL datasets demonstrates that StepPRM-RTL outperforms the best prior methods by over 10% in functional correctness and reasoning fidelity metrics. Ablation studies confirm that the combination of PRM-guided rewards and stepwise trajectory exploration is key to its performance. StepPRM-RTL generalizes across RTL languages and provides a scalable framework for high-fidelity, interpretable code generation, establishing a new standard for LLM-assisted hardware design automation.

Confidential environments such as Trusted Execution Environments (TEEs) are increasingly used to protect the data and models of machine learning applications from adversarial attacks. Frameworks like TEE-protected Neural Networks (NN) have been deployed for secure cloud-based inference. However, recent studies have revealed one kind of ciphertext side channels that exploit the encryption process within TEE environments, known as CipherSteal attacks. Specifically, when data is transferred into a TEE using encryption schemes such as AES, the resulting ciphertext patterns can be observed to infer input data. In this paper, we propose a series of methods named CipherShield to mitigate the ciphertext side-channel leakage and protect sensitive input data. It is a set of lightweight transformations that diffuse and decorrelate ciphertext without modifying the cryptography scheme. Our defenses, including block-based encryption, sparsity, and quantization, disrupt the per-address mapping patterns that ciphertext side-channels rely on to detect collisions while maintaining TEE compatibility and high throughput. The ciphertext hit rate, which reflects the amount of information leaked through ciphertext traces, drops from 50–80% to nearly zero across all evaluated datasets. On MNIST, CipherShield reduces classification accuracy from about 68% to as low as 2%. Evaluations on the Chest X-ray and CelebA datasets show similar reductions. Also, prototyping the block-based encryption in a TEE environment achieves markedly lower runtime than the original trace-based method, reducing encryption time by over 20x.

We present L2L, exploring end-to-end design optimization from logic to layout. The L2L framework includes logic, circuit, and layout stages. Logic exploration introduces two-stage transistor network synthesis. At the circuit stage, we propose two SMT models for transistor network synthesis: Connected-Diffusion (arbitrary, stack-height-bounded, multi-solution) and Grid-Scaffold (series-parallel). At the layout stage, an ILP-based flow co-optimizes circuit topology and double-height layouts, producing two 3-input P-class libraries (area- and metal-optimized). Block-level experiments demonstrate that full inclusion of 3-input P-class functions achieves up to 1.3% lower power, 5.6% higher performance, and 4.1% smaller area (average: 0.8%, 0.6%, 2.6%) outperforming the best prior baseline.

This paper presents the first self-evolved logic synthesis framework, which leverages Large Language Models (LLMs) in a multi-agent setup to autonomously improve the source code of ABC. Our approach builds upon recent work in LLM-driven code evolution and extends the idea to the substantially more complex monolithic ABC codebase. We bootstrap the process with established human-designed optimizations and external research code. And in each iteration, the agents propose and implement code modifications which are then validated for correctness and evaluated on standard benchmark circuits to provide quality-of-result (QoR) feedback. Over time, the framework organically discovers improvements beyond the initial heuristics and complete the coding evolution autonomously in the whole ABC repository, effectively learning-to-progress better synthesis tool.

This paper proposes the Stone-Skimming microarchitectural attack, the first page table walk (PTW)-based attack targeting large-scale sensitive memory applications. Stone-Skimming leverages the correlation among multiple signals to establish novel side channel attacks. We develop the first microarchitectural attack targeting DNA sequence reconstruction. Multiple PTW entries generated by the victim are cross-validated, enabling robust DNA reconstruction where traditional attacks fail. Moreover, we discover a new stateful side effect of PTW on prefetch instructions that can be exploited to break KASLR, even with KPTI on. We also introduce the early-instruction-fetch (early-IF) attack capable of bypassing LFENCE and CPUID defense.

Recent AI-driven inverse design approaches have shown promise in synthesizing complex electromagnetic (EM) structures for radio- frequency (RF) circuits. However, existing methods suffer from two fundamental limitations: random topology generation often pro- duces physically infeasible layouts, and pixel-based representations encode only topology while ignoring geometric dimensions, forc- ing complete dataset regeneration and model retraining whenever layout scale changes. To address these issues, we propose PeRIFi, a physics-constrained and geometry-aware inverse design frame- work built on three key innovations. (1) Feasibility-aware param- eterization integrates B-splines, which guarantee direct-current (DC) connectivity, with level-set representations that enable flexible geometric variation, ensuring 100% physically feasible structure generation. (2) Explicit geometric encoding decouples topol- ogy from geometric dimensions, allowing a single surrogate model to generalize across multiple layout scales without regenerating datasets. (3) High-dimensional optimization employs Particle Swarm Optimization tailored to the proposed 268-dimensional fea- sible design space. Experimental results demonstrate substantial data-efficiency gains: with only 5k training samples, PeRIFi attains 73% lower MSE and a 6.7% higher 𝑅^2 than a pixel-based baseline trained on 20k samples. Furthermore, PeRIFi reduces optimization cost by 22.19%–34.71% and lowers prediction error (MAE) by 58.2% compared with state-of-the-art methods, enabling more accurate and scalable RF inverse design.

Logic synthesis compilers play an indispensable role in FPGA design, translating register-transfer-level (RTL) descriptions into gate-level netlists. Defects in these compilers may compromise the security of the final hardware implementations. Existing testing methods often produce redundant test cases, which limits their ability to effectively explore compiler defects. To address this problem, we propose RL4HDL, a new method that uses reinforcement learning to guide logic synthesis compiler testing. Comprehensive experiments conducted over a three-month period demonstrate the practical effectiveness of our approach: we discovered 20 unique defects, including 12 previously unreported ones, all of which have been confirmed by the official developers.

Learning Parity with Noise (LPN) has emerged as a promising foundational primitive for post-quantum cryptography (PQC). However, existing LPN accelerators primarily optimize isolated computation while overlooking execution flow and suffering from data transfer bottlenecks. Recent advances in AI accelerators have demonstrated remarkable capabilities attributed to their novel architecture paradigms. Inspired by this insight, this work presents LHPA, the first AI-inspired hardware accelerator for LPN acceleration on FPGAs. LHPA implements a heterogeneous architecture comprising configurable hardware engines. Then, LHPA employs a stage-level scheduling strategy and establishes a bandwidth-oriented performance model. LHPA achieves a 52.80x performance gain over the state-of-the-art LPN architecture.

Floating-point multiply-accumulate (FPMAC) is crucial in scientific computing, machine learning, and graphics but remains a major performance and energy bottleneck. Conventional IEEE-754 FP-FMA schemes optimize single multiply-add fusion but overlook long-chain MAC patterns in GEMM, leading to redundant rounding and normalization, accumulated numerical error, and high delay and power overhead from wide carry-propagate adders (CPAs). We propose Factored-FPMAC (F-FPMAC), which employs 4:2 carry-save adders (CSAs) and CSA-based redundant representation inside systolic arrays to eliminate CPAs from processing elements and defer normalization to a unified post-processing stage. To prevent accumulated intermediate value overflow (AIVO) under deferred normalization, we introduce a lightweight hierarchical risk-aware boundary protection mechanism. To further reduce register overhead from redundant representation, we replace per-PE dual buffers with an array-shared buffer pool. Experimental results indicate that F-FPMAC reduces critical-path delay by 61.9%, lowers power consumption by 22.6%, improves energy efficiency by 3×, achieves nearly two orders of magnitude lower numerical error, and decreases overflow events by up to 44.5%.

With the growing deployment of large language models (LLMs), LLM inference cost has become a key challenge. Pruning techniques that introduce sparsity into weight matrices can accelerate inference. However, maintaining model quality typically limits pruning to moderate unstructured sparsity (around 50\%). At these sparsity levels, none of the existing GPU kernels for sparse matrix multiplication (SpMM) can outperform their dense counterparts. This paper proposes an efficient GPU inference method for LLMs with moderate sparsity. We propose a three-layer matrix storage format comprising: (i) a Sparse-TC layer enabling sparse tensor cores to accelerate SpMM; (ii) a Slot-Filling layer using parallel differential distance for matrix compression while supporting low-cost on-chip decoding; (iii) a lightweight Residual Layer ensuring correct SpMM computation. Building on this format, we design a SpMM kernel that jointly utilizes sparse tensor cores and CUDA cores. This design enables an efficient execution pipeline and overlaps on-chip computation with memory access. Evaluations show that our work is the first to outperform dense matrix multiplication on modern GPUs equipped with high-bandwidth memory (HBM). It achieves up to 1.64× kernel-level speedup over SpInfer (EuroSys'25, Best paper) and up to 1.41× end-to-end speedups over FlashLLM (VLDB'24). Our source code: https://anonymous.4open.science/r/spmm-32E1.

Log schema extraction, the process of deriving human-readable templates that support clear log understanding from massive volumes of log data, is fundamental for automated debugging and performance analysis across modern Electronic Design Automation (EDA) tool chains. The challenge is amplified in advanced design flows, where logs interweave command scripts, multi-stage progress reports, timing updates, and deeply nested performance tables, rendering manual regular-expression design brittle and unscalable to evolving tool versions. We introduce SchemaCoder, a fully-automated LLM-driven schema extraction framework that constructs structured log schemas by synthesizing reusable parser code, enabling robust handling of arbitrary unstructured log files and complex EDA tool logs without manual regular-expression design. At its core, SchemaCoder uses a novel Question-Tree (Q-Tree) pattern code generation process to identify pattern codes and utilizes the extracted raw contents to drive a textual residual evolutionary optimizer in the inner loop without relying on a gold labeled dataset. In the outer loop, a residual Q-Tree boosting mechanism identifies additional pattern codes and iteratively refines the parser code. On EDA tool logs from OpenROAD and commercial tools, the structured log schema generated by SchemaCoder enables an average 11.7% improvement in agentic EDA tool log analysis QA tasks (pass@1) over a strong commercial baseline. SchemaCoder also achieves up to 7.3% improvement in the average scores and outperforms state-of-the-art baselines in 9 of 14 applications on LogHub-2.0. We will open-source the code and the EDA tool log QA benchmark for reproducibility upon acceptance.

Advanced 3D and 3.5D IC packaging significantly improves integration density but elevates thermal management challenges due to cross-layer heat coupling and complex cooling structures. Traditional solvers deliver high fidelity but are too slow for iterative design flows, while existing learning-based methods either fail to capture inter-die thermal coupling or treat cooling structures as static components, limiting their applicability in real packaging co-design scenarios. In this work, we introduce COOL, a cooling-aware point transformer framework that represents heterogeneous assemblies (dies, interposers, TIMs, heat spreaders) as annotated 3D point clouds embedding geometric, material, and power attributes. COOL explicitly encodes geometric boundaries and cooling structures, and introduces a physics-informed boundary condition (PI-BC) loss to enforce thermal consistency at material interfaces and cooling boundaries. Extensive experiments demonstrate that COOL achieves a remarkable 2.4% NMAE on our constructed benchmark of multi-package thermal designs, substantially outperforming existing learning-based approaches while providing over 15.7× speedup compared to commercial FEM solvers.

Weights in neural networks (NNs) are signed. Resistive Random Access Memory (RRAM), though a promising computing in-memory (CiM) for NN acceleration, is inherently unipolar as the conductance can only be positive, making it challenging to represent signed weights.Existing mainstream solutions utilize a differential pair of RRAM cells for representing a signed weight, which double the array size and significantly increase peripheral circuit cost, limiting the scalability and energy efficiency of CiM accelerators.In this work, instead of assigning a specific sign to each weight, we treat each column of the CiM crossbar as a unit and assign an identical sign to the entire column. To do this, we propose a Sign-Align Training and Mapping (SATM) framework that regularizes the network during training so that all weights mapped to the same column of a CiM crossbar share an identical sign. A per-column Sign Register (PSR) is added to the array's periphery to store the learned 1-bit sign configuration for each respective column. The experimental results show that the proposed SATM achieves up to 49.3% reduction in area overhead and up to 60.7% reduction in energy consumption for AlexNet, ResNet18, VGG16, ResNet50, and ViT-Base models compared to differential-pair implementations.

Hardware design verification is essential for ensuring the functional correctness of electronic designs. Recent advances have explored using Large Language Models (LLMs) to automate hardware testbench synthesis. However, existing approaches primarily target single hardware modules and often fail to generalize to complex, system-level designs. As design complexity increases, both the LLM-generated testbench and the reference design are more likely to exhibit correlated or compensating errors, often producing false-positive outcomes that obscure true functional violations. To tackle these challenges, we propose ReflectBench, an agentic framework for automated system-level hardware design verification with logic analysis, consensus-based validation, feedback self-reflection, and testbench self-correction. To further minimize manual effort in constructing knowledge bases or preparing examples, we devise Self-Reflective Domain Knowledge Mining, an automated approach for constructing an effective retrieval database aligned with hardware semantics. We develop ReflectVDB, a benchmark consisting of 53 system-level hardware designs for evaluating LLM-based verification frameworks. Experimental results show that our approach outperforms SOTA framework ConfiBench on both ReflectVDB and AutoBench datasets, achieving 7.6\% and 4.5\% improvement in terms of testbench generation success rate, and 3.8\% and 1.2\% improvement in terms of coverage rate. The framework and ReflectVDB benchmark are open-sourced at https://anonymous.4open.science/r/ReflectBench/.

Physical design is a critical step in the electronic design automation (EDA) process, where the gate-level netlist from logic synthesis is converted into a GDS-II file. Recently, AI methods have been increasingly employed to address challenges in physical design. This paper proposes a new paradigm that integrates routing metric evaluation and optimization on chip layouts, forming a ``Generate–Evaluate–Optimize–Generate'' (GEOG) closed-loop. In our experiments, the pre-routing generation model achieves an mean relative error (MRE) of only 1%, with a mean absolute error (MAE) below one movement unit. Post-processing reduces both MRE and MAE to zero while ensuring connectivity. The evaluation model performs comparably to iSTA on the test set, with a 336× speedup. Furthermore, the optimization strategy effectively improves wirelength, delay, slew, R, and C by 10.49%, 13.03%, 14.85%, 10.51%, and 6.46%, respectively, and produces routing results superior to commercial tools in key metrics.

3D In-memory Computing (IMC) chips, with high density and bandwidth, offer a promising solution for AI workloads but suffer from thermal instability, which degrades weight precision and system throughput. This work proposes a cross-layer thermal stability strategy (TSS) and validates it on the first 3D eFlash analog IMC prototype with hybrid bonding, integrating a 12nm logic die and a 28nm eFlash die (36MB). TSS consists of: (1) a physics-guided thermal model achieving a kullback-leibler divergence of 0.088; (2) a temperature-insensitive differential programming (TIDP) scheme that stabilizes weights from –30°C to 60°C; and (3) an adaptive temperature calibration (ATC) algorithm that reduces output error standard deviation by 60.7%. With TSS, ResNet-18 and DCCRN maintain robust inference on the 3D eFlash IMC SoC across –15°C to 75°C with less than 10% degradation in end-to-end task accuracy. This is the first demonstration of thermally resilient analog IMC on a commercial-grade 3D SoC, paving the way for reliable AI deployment under dynamic thermal conditions.

Flash wear raises raw bit error rate (RBER), limiting SSD lifetime by TBW or P/E cycles. We present SSD Reforge, which dynamically strengthens protection near end‑of‑life by adding intra‑device parity, allowing more lifetime. To handle inter‑block reliability heterogeneity, we build an RBER‑based error‑probability model and derive parity stripe grouping as a combinatorial optimization problem. We design Reliability‑Aware Striping (RAS) for efficient grouping and Stripe UPER Leveling (SUPERL) to sustain RAS during subsequent writes. Implemented in FEMU and evaluated with real I/O traces, SSD Reforge increases user TBW by up to 40% on average versus traditional mode at the lifetime limit, significantly extending SSD lifespan.

Bird's-eye-view (BEV) fusion of multi-modal sensor data is a leading approach for high-performance 3D object detection. However, state-of-the-art models rarely exceed 10 FPS even on powerful GPUs, limiting their use in real-time applications. In this paper, we present a neural architecture search (NAS) framework that identifies models achieving both high accuracy and real-time inference. The search space is explicitly designed with hardware constraints to balance accuracy and computational efficiency on resource-limited platforms. To better align LiDAR and camera features in the BEV conversion module, we introduce a lightweight depth estimation network and a LiDAR–camera cross-attention mechanism that enhances detection accuracy with minimal overhead. On the challenging nuScenes benchmark, our model achieves 70.1% mAP, which represents a 2.3% point improvement over the baseline model, while running at 35.6 FPS on the Nvidia Jetson AGX Orin, demonstrating its suitability for real-time autonomous driving.

General matrix–matrix multiplication (GEMM) remains the dominant compute kernel in transformer-based large language model (LLM) inference. However, large-scale matrices exhibiting irregular sparsity fundamentally limit throughput and energy efficiency in existing systems. To address these challenges, we propose PEACE, an energy-aware matrix compression framework for accelerating GEMM operations at the processing element (PE)-array granularity. PEACE comprises a novel matrix compression algorithm, PEACE-Alg, which reorganizes large-scale matrices into hardware-friendly compressed formats by exploiting the column-wise energy distribution. To support PEACE-Alg, we design a hardware microarchitecture, PEACE-Hw, that integrates RISC-V ISA extensions with a table-metadata fetcher and a metadata-driven operand loader to feed a reconfigurable systolic PE array, and a dedicated partial-sum adder for efficiently merging intermediate results. Experimental results show that PEACE occupies 2.705 mm^2 in a 14 nm ASIC and delivers a peak INT8 throughput of 88 GOPS/W. PEACE achieves 1.60×-1.67× speedup over a RISC-V core baseline across 14 transformer-based LLMs. Compared with state-of-the-art designs, PEACE provides 4.4× higher PE density, 1.79× average speedup and 2.53× energy efficiency.

Spiking Neural Networks (SNNs) promise exceptional energy efficiency for neuromorphic computing through event-driven processing. However, unlocking their full potential requires navigating a complex, strongly coupled design space of network topology and temporal neural encoding. Existing SNN Neural Architecture Search (NAS) frameworks typically decouple these dimensions, focusing exclusively on topology search while relying on manual, fixed encoding schemes. This limitation leaves a vast portion of the design space unexplored, resulting in sub-optimal energy-accuracy trade-offs. To bridge this gap, we present ACE-NAS, the first zero-cost NAS framework that automates the co-design of SNN architecture and encoding mechanisms. Addressing the challenge of "encoding-blind" proxies, we introduce Jacob_cov, a novel Jacobian-based spectral metric that efficiently quantifies the temporal discriminability of different encoding schemes without training. ACE-NAS integrates Jacob_cov with structural proxies (ZiCo) into a hardware-aware, multi-objective evolutionary search strategy. On CIFAR-10, ACE-NAS achieves 92.95% accuracy, effectively identifying Pareto-optimal designs that balance high performance with minimal spike activity. By automating the joint optimization of structure and dynamics, ACE-NAS delivers an orders-of-magnitude reduction compared to standard training-based NAS and a 7× speedup over state-of-the-art efficient SNN-NAS methods (e.g., AutoSNN).